XC3S50 Datasheet, PDF (94/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: Pinout Descriptions
DUAL Type: Dual-Purpose Configuration and
I/O Pins
These pins serve dual purposes. The user-I/O pins are tem-
porarily borrowed during the configuration process to load
configuration data into the FPGA. After configuration, these
pins are then usually available as a user I/O in the applica-
tion. If a pin is not applicable to the specific configuration
mode—controlled by the mode select pins M2, M1, and
M0—then the pin behaves as an I/O-type pin.
There are 12 dual-purpose configuration pins on every
package, six of which are part of I/O Bank 4, the other six
part of I/O Bank 5. Only a few of the pins in Bank 4 are used
in the Serial configuration modes.
See “Configuration” under Functional Description (Module 2
of the Spartan-3 data sheet).
See “Pin Behavior During Configuration, page 15”.
Serial Configuration Modes
This section describes the dual-purpose pins used during
either Master or Slave Serial mode. See Table 7 for Mode
Select pin settings required for Serial modes. All such pins
are in Bank 4 and powered by VCCO_4.
In both the Master and Slave Serial modes, DIN is the serial
configuration data input. The D1-D7 inputs are unused in
serial mode and behave like general-purpose I/O pins.
In all the cases, the configuration data is synchronized to
the rising edge of the CCLK clock signal.
The DIN, DOUT, and INIT_B pins can be retained in the
application to support reconfiguration by setting the Persist
bitstream generation option. However, the serial modes do
not support device readback.
Table 3: Dual-Purpose Pins Used in Master or Slave Serial Mode
Pin Name Direction
Description
DIN
Input
Serial Data Input:
During the Master or Slave Serial configuration modes, DIN is the serial configuration data
input, and all data is synchronized to the rising CCLK edge. After configuration, this pin is
available as a user I/O.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User
mode.
DOUT
Output
Serial Data Output:
In a multi-FPGA design where all the FPGAs use serial mode, connect the DOUT output of
one FPGA—in either Master or Slave Serial mode—to the DIN input of the next FPGA—in
Slave Serial mode—so that configuration data passes from one to the next, in daisy-chain
fashion. This “daisy chain” permits sequential configuration of multiple FPGAs.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User
mode.
INIT_B
Bidirectional
(open-drain)
Initializing Configuration Memory/Configuration Error:
Just after power is applied, the FPGA produces a Low-to-High transition on this pin
indicating that initialization (i.e., clearing) of the configuration memory has finished. Before
entering the User mode, this pin functions as an open-drain output, which requires a pull-up
resistor in order to produce a High logic level. In a multi-FPGA design, tie (wire AND) the
INIT_B pins from all FPGAs together so that the common node transitions High only after
all of the FPGAs have been successfully initialized.
Externally holding this pin Low beyond the initialization phase delays the start of
configuration. This action stalls the FPGA at the configuration step just before the mode
select pins are sampled.
During configuration, the FPGA indicates the occurrence of a data (i.e., CRC) error by
asserting INIT_B Low.
This signal is located in Bank 4 and its output voltage determined by VCCO_4.
The BitGen option Persist permits this pin to retain its configuration function in the User
mode.
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
7
Product Specification
1-800-255-7778