XC3S50 Datasheet, PDF (17/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 1.2V FPGA Family: Functional Description
R
.
Left-Hand SLICEM
(Logic or Distributed RAM
or Shift Register)
Right-Hand SLICEL
(Logic Only)
COUT
CLB
SLICE
X1Y1
Switch
Matrix
COUT
SHIFTOUT
SHIFTIN
SLICE
X0Y1
SLICE
X0Y0
SLICE
X1Y0
CIN
Interconnect
to Neighbors
CIN
DS099-2_05_040703
Figure 5: Arrangement of Slices within the CLB
CLB Overview
The Configurable Logic Blocks (CLBs) constitute the main
logic resource for implementing synchronous as well as
combinatorial circuits. Each CLB comprises four intercon-
nected slices, as shown in Figure 5. These slices are
grouped in pairs. Each pair is organized as a column with an
independent carry chain.
The nomenclature that the FPGA Editor — part of the Xilinx
development software — uses to designate slices is as fol-
lows: The letter "X" followed by a number identifies columns
of slices. The "X" number counts up in sequence from the
left side of the die to the right. The letter "Y" followed by a
number identifies the position of each slice in a pair as well
as indicating the CLB row. The "Y" number counts slices
starting from the bottom of the die according to the
sequence: 0, 1, 0, 1 (the first CLB row); 2, 3, 2, 3 (the sec-
ond CLB row); etc. Figure 5 shows the CLB located in the
lower left-hand corner of the die. Slices X0Y0 and X0Y1
make up the column-pair on the left where as slices X1Y0
and X1Y1 make up the column-pair on the right. For each
CLB, the term “left-hand” (or SLICEM) is used to indicated
the pair of slices labeled with an even "X" number, such as
X0, and the term “right-hand” (or SLICEL) designates the
pair of slices with an odd "X" number, e.g., X1.
Elements Within a Slice
All four slices have the following elements in common: two
logic function generators, two storage elements, wide-func-
tion multiplexers, carry logic, and arithmetic gates, as
shown in Figure 6. Both the left-hand and right-hand slice
pairs use these elements to provide logic, arithmetic, and
ROM functions. Besides these, the left-hand pair supports
two additional functions: storing data using Distributed RAM
and shifting data with 16-bit registers. Figure 6 is a diagram
of the left-hand slice; therefore, it represents a superset of
the elements and connections to be found in all slices. See
Function Generator, page 12 for more information.
The RAM-based function generator — also known as a
Look-Up Table or LUT — is the main resource for imple-
menting logic functions. Furthermore, the LUTs in each
left-hand slice pair can be configured as Distributed RAM or
a 16-bit shift register. For information on the former, see
XAPP464: Using Look-Up Tables as Distributed RAM in
Spartan-3 FPGAs; for information on the latter, refer to
XAPP465: Using Look-Up Tables as Shift Registers (SRL16)
in Spartan-3 FPGAs. The function generators located in the
upper and lower portions of the slice are referred to as the
"G" and "F", respectively.
The storage element, which is programmable as either a
D-type flip-flop or a level-sensitive latch, provides a means
for synchronizing data to a clock signal, among other uses.
The storage elements in the upper and lower portions of the
slice are called FFY and FFX, respectively.
Wide-function multiplexers effectively combine LUTs in
order to permit more complex logic operations. Each slice
has two of these multiplexers with F5MUX in the lower por-
tion of the slice and FXMUX in the upper portion. Depend-
ing on the slice, FXMUX takes on the name F6MUX,
F7MUX, or F8MUX. For more details on the multiplexers,
see XAPP466: Using Dedicated Multiplexers in Spartan-3
FPGAs.
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DS099-2 (v1.2) July 11, 2003
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