XC3S50 Datasheet, PDF (72/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: DC and Switching Characteristics
Core Logic Timing
Table 23: CLB Timing
Speed Grade
-5
-4
Symbol
Description
Min
Max
Min
Max
Clock-to-Output Times
T_CKO
When reading from the FFX (FFY) Flip-Flop,
-
0.67
-
0.77
the time from the active transition at the CLK
input to data appearing at the XQ (YQ) output
Setup Times
T_DYCK
Time from the setup of data at the D input to
0.08
-
0.09
-
the active transition at the CLK input of FFX
T_DXCK
Time from the setup of data at the D input to
0.08
-
0.09
-
the active transition at the CLK input of FFY
Hold Times
T_CKDY
Time from the active transition at FFY’s CLK
0.01
-
0.01
-
input to the point where data is last held at the
D input
T_CKDX
Time from the active transition at FFX’s CLK
0.01
-
0.01
-
input to the point where data is last held at the
D input
Clock Timing
T_CH
The High pulse width of the CLB’s CLK signal 0.76
-
0.87
-
T_CL
The Low pulse width of the CLK signal
0.76
-
0.87
-
F_TOG
Maximum toggle frequency (for export control)
-
500
-
500
Propagation Times
T_ILO
The time it takes for data to travel from the
-
0.65
-
0.75
CLB’s F (G) input to input to the X (Y) output
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 5.
Units
ns
ns
ns
ns
ns
ns
ns
MHz
ns
DS099-3 (v1.3) March 4, 2004
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