XC3S50 Datasheet, PDF (53/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: DC and Switching Characteristics
Table 9: DC Characteristics of User I/Os Using Single-Ended Standards
Signal Standard and
Current Drive Attribute
(mA)
Test Conditions
I_OL
I_OH
(mA)
(mA)
GTL
32
-
GTL_DCI
Note 3
Note 3
GTLP
36
-
GTLP_DCI
Note 3
Note 3
HSTL_I
8
–8
HSTL_I_DCI
Note 3
Note 3
HSTL_III
24
–8
HSTL_III_DCI
Note 3
Note 3
HSTL_I_18
8
–8
HSTL_I_DCI_18
Note 3
Note 3
HSTL_II_18
16
–16
HSTL_II_DCI_18
Note 3
Note 3
HSTL_III_18
24
–8
HSTL_III_DCI_18
Note 3
Note 3
LVCMOS12⁽⁴⁾
2
2
–2
4
4
–4
6
6
–6
LVCMOS15⁽⁴⁾
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12
12
–12
LVDCI_15,
LVDCI_DV2_15
Note 3
Note 3
LVCMOS18⁽⁴⁾
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16
16
–16
LVDCI_18,
LVDCI_DV2_18
Note 3
Note 3
LVCMOS25^(4,5)
2
2
–2
4
4
–4
6
6
–6
8
8
–8
12
12
–12
16
16
–16
24
24
–24
LVDCI_25,
LVDCI_DV2_25
Note 3
Note 3
R
Logic Level Characteristics
V_OL
V_OH
Max (V)
Min (V)
0.4
-
0.6
-
0.4
V_CCO - 0.4
0.4
V_CCO - 0.4
0.4
V_CCO - 0.4
0.4
V_CCO - 0.4
0.4
V_CCO - 0.4
0.4
V_CCO - 0.4
0.4
V_CCO - 0.4
0.4
V_CCO - 0.4
0.4
V_CCO - 0.4
6
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DS099-3 (v1.3) March 4, 2004
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