XC3S50 Datasheet, PDF (2/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

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DS099-1 (v1.2) December 24, 2003
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Spartan-3 FPGA Family:
Introduction and Ordering
Information
0 0 _{Advance Product Specification}
Introduction
The Spartan™-3 family of Field-Programmable Gate Arrays
is specifically designed to meet the needs of high volume,
cost-sensitive consumer electronic applications. The
eight-member family offers densities ranging from 50,000 to
five million system gates, as shown in Table 1.
The Spartan-3 family builds on the success of the earlier
Spartan-IIE family by increasing the amount of logic
resources, the capacity of internal RAM, the total number of
I/Os, and the overall level of performance as well as by
improving clock management functions. Numerous
enhancements derive from state-of-the-art Virtex™-II tech-
nology. These Spartan-3 enhancements, combined with
advanced process technology, deliver more functionality
and bandwidth per dollar than was previously possible, set-
ting new standards in the programmable logic industry.
Because of their exceptionally low cost, Spartan-3 FPGAs
are ideally suited to a wide range of consumer electronics
applications, including broadband access, home network-
ing, display/projection and digital television equipment.
The Spartan-3 family is a superior alternative to mask pro-
grammed ASICs. FPGAs avoid the high initial cost, the
lengthy development cycles, and the inherent inflexibility of
conventional ASICs. Also, FPGA programmability permits
design upgrades in the field with no hardware replacement
necessary, an impossibility with ASICs.
Features
• Revolutionary 90-nanometer process technology
• Very low cost, high-performance logic solution for
high-volume, consumer-oriented applications
- Densities as high as 74,880 logic cells
- 326 MHz system clock rate
- Three power rails: for core (1.2V), I/Os (1.2V to
3.3V), and auxiliary purposes (2.5V)
• SelectIO™ signaling
- Up to 784 I/O pins
- 622 Mb/s data transfer rate per I/O
- Seventeen single-ended signal standards
- Seven differential signal standards including LVDS
- Termination by Digitally Controlled Impedance
- Signal swing ranging from 1.14V to 3.45V
- Double Data Rate (DDR) support
• Logic resources
- Abundant logic cells with shift register capability
- Wide multiplexers
- Fast look-ahead carry logic
- Dedicated 18 x 18 multipliers
- JTAG logic compatible with IEEE 1149.1/1532
specifications
• SelectRAM™ hierarchical memory
- Up to 1,872 Kbits of total block RAM
- Up to 520 Kbits of total distributed RAM
• Digital Clock Manager (up to four DCMs)
- Clock skew elimination
- Frequency synthesis
- High resolution phase shifting
• Eight global clock lines and abundant routing
• Fully supported by Xilinx ISE development system
- Synthesis, mapping, placement and routing
• MicroBlaze processor, PCI, and other cores
Table 1: Summary of Spartan-3 FPGA Attributes
Device
System
Gates
Logic
Cells
CLB Array
(One CLB = Four Slices)
Rows Columns Total CLBs
Distributed Block RAM
RAM (bits¹)
(bits¹)
Dedicated
Multipliers
DCMs
Maximum
Maximum Differential
User I/O I/O Pairs
XC3S50
50K
1,728
16
12
192
12K
72K
4
2
124
56
XC3S200
200K 4,320
24
20
480
30K
216K
12
4
173
76
XC3S400
400K 8,064
32
28
896
56K
288K
16
4
264
116
XC3S1000
1M
17,280 48
40
1,920
120K
432K
24
4
391
175
XC3S1500 1.5M 29,952 64
52
3,328
208K
576K
32
4
487
221
XC3S2000
2M
46,080 80
64
5,120
320K
720K
40
4
565
270
XC3S4000
4M
62,208 96
72
6,912
432K
1,728K
96
4
712
312
XC3S5000
5M
74,880 104
80
8,320
520K
1,872K
104
4
784
344
Notes:
1. By convention, one Kb is equivalent to 1,024 bits.
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS099-1 (v1.2) December 24, 2003
www.xilinx.com
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Advance Product Specification
1-800-255-7778