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Spartan-3 1.2V FPGA Family: Functional Description
3.3V-Tolerant Configuration Interface
It is possible to achieve 3.3V-tolerance at the configuration
interface simply by adding a few external resistors. This
approach may prove useful when it is undesirable to switch
the VCCO_4 and VCCO_5 voltages from 2.5V to 3.3V after
configuration.
The 3.3V-tolerance is implemented as follows (a similar
approach can be used for other supply voltage levels):
First, to power the Dual-Purpose configuration pins, apply
3.3V to the VCCO_4 and (as needed) the VCCO_5 lines.
This scales the output voltages and input thresholds associ-
ated with these pins so that they become 3.3V-compatible.
Second, to power the Dedicated configuration pins, apply
2.5V to the V_CCAUX lines (the same as for the standard
interface). In order to achieve 3.3V-tolerance, the Dedicated
inputs will require series resistors that limit the incoming
current to 10mA or less. The Dedicated outputs will need
pull-up resistors to ensure adequate noise margin when the
FPGA is driving a High logic level into another device’s 3.3V
receiver. Choose a power regulator or supply that can toler-
ate reverse current on the V_CCAUX lines.
Configuration Modes
Spartan-3 supports the following five configuration modes:
• Slave Serial mode
• Master Serial mode
• Slave Parallel mode
• Master Parallel mode
• Boundary-Scan (JTAG) mode (IEEE 1532/IEEE
1149.1)
Slave Serial Mode
In Slave Serial mode, the FPGA receives configuration data
in bit-serial form from a serial PROM or other serial source
of configuration data. The FPGA on the far right of Figure 20
is set for the Slave Serial mode. The CCLK pin on the FPGA
is an input in this mode. The serial bitstream must be setup
at the DIN input pin a short time before each rising edge of
the externally generated CCLK.
Multiple FPGAs can be daisy-chained for configuration from
a single source. After a particular FPGA has been config-
ured, the data for the next device is routed internally to the
DOUT pin. The data on the DOUT pin changes on the rising
edge of CCLK.
3.3V
2.5V
2.5V
V_CC
V_CCO
V_CCJ
D0
Platform
Flash PROM
2.5V
XCF0xS
or
XCFxxP
CE
OE/RESET
CF
CLK
GND
All
4.7KΩ
V_CCO Bank 4
V_CCAUX V_CCINT
1.2V
DIN
DOUT
Spartan-3
FPGA
Master
M0
M1
M2
DONE
INIT_B
PROG_B
CCLK
GND
2.5V
V_CCO Bank 4
V_CCAUX V_CCINT
1.2V
DIN
Spartan-3
FPGA
2.5V
Slave
M0
M1
M2
DONE
INIT_B
PROG_B
CCLK
GND
DS099_23_041103
Notes:
1. There are two ways to use the DONE line. First, one may set the BitGen option DriveDone to "Yes" only for the
last FPGA to be configured in the chain shown above (or for the single FPGA as may be the case). This enables
the DONE pin to drive High; thus, no pull-up resistor is necessary. DriveDone is set to "No" for the remaining
FPGAs in the chain. Second, DriveDone can be set to "No" for all FPGAs. Then all DONE lines are open-drain
and require the pull-up resistor shown in grey. In most cases, a value between 3.3KΩ to 4.7KΩ is sufficient.
However, when using DONE synchronously with a long chain of FPGAs, cumulative capacitance may
necessitate lower resistor values (e.g. down to 330Ω) in order to ensure a rise time within one clock cycle.
2. For information on how to program the FPGA using 3.3V signals and power, see 3.3V-Tolerant Configuration
Interface.
Figure 20: Connection Diagram for Master and Slave Serial Configuration
DS099-2 (v1.2) July 11, 2003
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