XC3S50 Datasheet, PDF (85/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: DC and Switching Characteristics
R
TCK
(Input)
TMS
(Input)
TDI
(Input)
TDO
(Output)
T_TMSTCK
T_TDITCK
T_TCKTMS
T_TCKTDI
T_CCH
T_CCL
1/F_TCK
T_TCKTDO
Figure 8: JTAG Waveforms
DS099_06_040703
Table 37: Timing for the JTAG Test Access Port
All Speed Grades
Symbol
Description
Min
Max
Clock-to-Output Times
T_TCKTDO
The time from the falling transition on the TCK pin
-
to data appearing at the TDO pin
11.0
Setup Times
T_TDITCK
The time from the setup of data at the TDI pin to
5.0
-
the rising transition at the TCK pin
T_TMSTCK
The time from the setup of a logic level at the TMS
5.0
-
pin to the rising transition at the TCK pin
Hold Times
T_TCKTDI
The time from the rising transition at the TCK pin
0
-
to the point when data is last held at the TDI pin
T_TCKTMS
The time from the rising transition at the TCK pin
0
-
to the point when a logic level is last held at the
TMS pin
Clock Timing
T_CCH
The High pulse width at the TCK pin
5
-
T_CCL
The Low pulse width at the TCK pin
5
-
F_TCK
Frequency of the TCK signal
-
33
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 5.
Units
ns
ns
ns
ns
ns
ns
ns
MHz
38
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DS099-3 (v1.3) March 4, 2004
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