XC3S50 Datasheet, PDF (186/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 FPGA Family: Pinout Descriptions
Table 37: FG1156 Package Pinout (Continued)
Bank
XC3S4000
Pin Name
XC3S5000
Pin Name
FG1156
Pin
Number
Type
VCCAUX HSWAP_EN HSWAP_EN
L11 CONFIG
VCCAUX M0
M0
AL4 CONFIG
VCCAUX M1
M1
AK4 CONFIG
VCCAUX M2
M2
AG8 CONFIG
VCCAUX PROG_B
PROG_B
D4 CONFIG
VCCAUX TCK
TCK
D31
JTAG
VCCAUX TDI
TDI
E4
JTAG
VCCAUX TDO
TDO
E31
JTAG
VCCAUX TMS
TMS
H27
JTAG
User I/Os by Bank
Table 38 indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks for the XC3S4000 in
the FG1156 package. Similarly, Table 39 shows how the
available user-I/O pins are distributed between the eight I/O
banks for the XC3S5000 in the FG1156 package.
Table 38: User I/Os Per Bank for XC3S4000 in FG1156 Package
I/O
Maximum
Package Edge
Bank
I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
90
79
0
2
7
Top
1
90
79
0
2
7
2
88
80
0
2
6
Right
3
88
79
0
2
7
4
90
73
6
2
7
Bottom
5
90
73
6
2
7
6
88
79
0
2
7
Left
7
88
79
0
2
7
GCLK
2
2
0
0
2
2
0
0
Table 39: User I/Os Per Bank for XC3S5000 in FG1156 Package
I/O
Maximum
Package Edge
Bank
I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
100
89
0
2
7
Top
1
100
89
0
2
7
2
96
87
0
2
7
Right
3
96
87
0
2
7
4
100
83
6
2
7
Bottom
5
100
83
6
2
7
6
96
87
0
2
7
Left
7
96
87
0
2
7
GCLK
2
2
0
0
2
2
0
0
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
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Product Specification
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