XC3S50 Datasheet, PDF (59/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: DC and Switching Characteristics
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Table 13: Pin-to-Pin Setup and Hold Times for the IOB Input Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Device
Min
Min
Units
Setup Times
T_PSDCM
When writing to the Input
Flip-Flop (IFF), the time
from the setup of data at
the Input pin to the active
transition at a Global
Clock pin. The DCM is in
use.
LVCMOS25⁽²⁾,
IOBDELAY = NONE⁽⁴⁾,
with DCM⁽⁵⁾
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
2.72
ns
2.72
ns
2.74
ns
2.76
ns
2.86
ns
2.98
ns
XC3S4000
3.06
ns
T_PSFD
When writing to IFF, the
time from the setup of
data at the Input pin to
an active transition at the
Global Clock pin. The
DCM is not in use.
LVCMOS25⁽²⁾,
IOBDELAY = NONE⁽⁴⁾,
without DCM
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
3.23
ns
2.43
ns
3.53
ns
3.52
ns
3.77
ns
4.15
ns
XC3S2000
4.34
ns
XC3S4000
4.53
ns
XC3S5000
4.90
ns
Hold Times
T_PHDCM
When writing to IFF, the
time from the active
transition at the Global
Clock pin to the point
when data must be held
at the Input pin. The
DCM is in use.
LVCMOS25⁽³⁾,
IOBDELAY = NONE⁽⁴⁾,
with DCM⁽⁵⁾
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
–1.81
ns
–1.81
ns
–1.81
ns
–1.81
ns
–1.81
ns
–1.81
ns
XC3S4000
–1.80
ns
T_PHFD
When writing to IFF, the
time from the active
transition at the Global
Clock pin to the point
when data must be held
at the Input pin. The
DCM is not in use.
LVCMOS25⁽³⁾,
IOBDELAY = NONE⁽⁴⁾,
without DCM
XC3S5000
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
–1.80
ns
–1.03
ns
–1.89
ns
–1.87
ns
–2.01
ns
–2.20
ns
–2.20
ns
XC3S4000
–2.24
ns
XC3S5000
–2.32
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set
forth in Table 5 and Table 8.
2. This setup time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the
data Input. If this is true of the Global Clock Input, subtract the appropriate adjustment from Table 16. If this is true of the data Input,
add the appropriate input adjustment from the same table.
3. This hold time requires adjustment whenever a signal standard other than LVCMOS25 is assigned to the Global Clock Input or the
data Input. If this is true of the Global Clock Input, add the appropriate Input adjustment from Table 16. If this is true of the data Input,
subtract the appropriate Input adjustment from the same table. When the hold time is negative, it is possible to change the data
before the clock’s active edge.
4. All numbers measured with no programmed input delay.
5. DCM output jitter is included in all measurements.
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