XC3S50 Datasheet, PDF (145/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: Pinout Descriptions
R
FG676: 676-lead Fine-pitch Ball Grid
Array
The 676-lead fine-pitch ball grid array package, FG676,
supports three different Spartan-3 devices, including the
XC3S1000, the XC3S1500, and the XC3S2000. All three
have nearly identical footprints but are slightly different due
to unconnected pins on the XC3S1000 and XC3S1500. For
example, because the XC3S1000 has fewer I/O pins, this
device has 98 unconnected pins on the FG676 package,
labeled as “N.C.” In Table 30 and Figure 14, these uncon-
nected pins are indicated with a black diamond symbol (‹).
The XC3S1500, however, has only two unconnected pins,
also labeled “N.C.” in the pinout table but indicated with a
black square symbol („).
All the package pins appear in Table 30 and are sorted by
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC1000, XC3S1500 and
XC3S2000 pinouts, then that difference is highlighted in
Table 30. If the table entry is shaded grey, then there is an
unconnected pin on either the XC3S1000 or XC3S1500 that
maps to a user-I/O pin on the XC3S2000. If the table entry
is shaded tan, then the unconnected pin on either the
XC3S1000 or XC3S1500 maps to a VREF-type pin on the
XC3S2000. If the other VREF pins in the bank all connect to
a voltage reference to support a special I/O standard, then
also connect the N.C. pin on the XC3S1000 or XC3S1500
to the same VREF voltage. This provides maximum flexibil-
ity as you could potentially migrate a design from the
XC3S1000 through to the XC3S2000 FPGA without chang-
ing the printed circuit board.
Pinout Table
Table 30: FG676 Package Pinout
XC3S1000
Bank Pin Name
0 IO
0 IO
0 IO
0 IO
0 N.C. (‹)
0 IO
0 IO
0 IO
0 IO
0 IO/VREF_0
0 IO/VREF_0
0 IO/VREF_0
0 IO_L01N_0/
VRP_0
XC3S1500
Pin Name
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/
VRP_0
XC3S2000
Pin Name
IO
IO
IO
IO
IO
IO
IO
IO
IO
IO/VREF_0
IO/VREF_0
IO/VREF_0
IO_L01N_0/
VRP_0
FG676
Pin
Number
A3
A5
A6
C4
C8
C12
E13
H11
H12
B3
F7
G10
E5
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
VREF
VREF
DCI
Table 30: FG676 Package Pinout (Continued)
XC3S1000
Bank Pin Name
XC3S1500
Pin Name
XC3S2000
Pin Name
FG676
Pin
Number
0 IO_L01P_0/ IO_L01P_0/ IO_L01P_0/
D5
VRN_0
VRN_0
VRN_0
0 IO_L05N_0 IO_L05N_0 IO_L05N_0
B4
0 IO_L05P_0/ IO_L05P_0/ IO_L05P_0/
A4
VREF_0
VREF_0
VREF_0
0 IO_L06N_0 IO_L06N_0 IO_L06N_0
C5
0 IO_L06P_0 IO_L06P_0 IO_L06P_0
B5
0 IO_L07N_0 IO_L07N_0 IO_L07N_0
E6
0 IO_L07P_0 IO_L07P_0 IO_L07P_0
D6
0 IO_L08N_0 IO_L08N_0 IO_L08N_0
C6
0 IO_L08P_0 IO_L08P_0 IO_L08P_0
B6
0 IO_L09N_0 IO_L09N_0 IO_L09N_0
E7
0 IO_L09P_0 IO_L09P_0 IO_L09P_0
D7
0 IO_L10N_0 IO_L10N_0 IO_L10N_0
B7
0 IO_L10P_0 IO_L10P_0 IO_L10P_0
A7
0 N.C. (‹)
IO_L11N_0 IO_L11N_0
G8
0 N.C. (‹)
IO_L11P_0 IO_L11P_0
F8
0 N.C. (‹)
IO_L12N_0 IO_L12N_0
E8
0 N.C. (‹)
IO_L12P_0 IO_L12P_0
D8
0 IO_L15N_0 IO_L15N_0 IO_L15N_0
B8
0 IO_L15P_0 IO_L15P_0 IO_L15P_0
A8
0 IO_L16N_0 IO_L16N_0 IO_L16N_0
G9
0 IO_L16P_0 IO_L16P_0 IO_L16P_0
F9
0 N.C. (‹)
IO_L17N_0 IO_L17N_0
E9
0 N.C. (‹)
IO_L17P_0 IO_L17P_0
D9
0 N.C. (‹)
IO_L18N_0 IO_L18N_0
C9
0 N.C. (‹)
IO_L18P_0 IO_L18P_0
B9
0 IO_L19N_0 IO_L19N_0 IO_L19N_0
F10
0 IO_L19P_0 IO_L19P_0 IO_L19P_0
E10
0 IO_L22N_0 IO_L22N_0 IO_L22N_0
D10
0 IO_L22P_0 IO_L22P_0 IO_L22P_0
C10
0 N.C. (‹)
IO_L23N_0 IO_L23N_0
B10
0 N.C. (‹)
IO_L23P_0 IO_L23P_0
A10
0 IO_L24N_0 IO_L24N_0 IO_L24N_0
G11
0 IO_L24P_0 IO_L24P_0 IO_L24P_0
F11
0 IO_L25N_0 IO_L25N_0 IO_L25N_0
E11
0 IO_L25P_0 IO_L25P_0 IO_L25P_0
D11
0 N.C. (‹)
IO_L26N_0 IO_L26N_0
B11
0 N.C. (‹)
IO_L26P_0/ IO_L26P_0/ A11
VREF_0
VREF_0
0 IO_L27N_0 IO_L27N_0 IO_L27N_0
G12
0 IO_L27P_0 IO_L27P_0 IO_L27P_0
H13
0 IO_L28N_0 IO_L28N_0 IO_L28N_0
F12
0 IO_L28P_0 IO_L28P_0 IO_L28P_0
E12
0 IO_L29N_0 IO_L29N_0 IO_L29N_0
B12
0 IO_L29P_0 IO_L29P_0 IO_L29P_0
A12
Type
DCI
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
I/O
I/O
I/O
I/O
I/O
I/O
58
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