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Spartan-3 1.2V FPGA Family: Functional Description
R
PSINCDEC
PSEN
PSCLK
CLKIN
CLKFB
RST
DCM
Phase
Shifter
PSDONE
DLL
Status
Logic
DFS
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
CLKFX
CLKFX180
LOCKED
8
STATUS [7:0]
Clock
Distribution
Delay
DS099-2_07_040103
Figure 13: DCM Functional Blocks and Associated Signals
The DCM has four functional components: the
Delay-Locked Loop (DLL), the Digital Frequency Synthe-
sizer (DFS), the Phase Shifter (PS), and the Status Logic.
Delay-Locked Loop (DLL)
The most basic function of the DLL component is to elimi-
nate clock skew. The main signal path of the DLL consists of
an input stage, followed by a series of discrete delay ele-
ments or taps, which in turn leads to an output stage. This
Each component has its associated signals, as shown in
Figure 13.
path together with logic for phase detection and control
forms a system complete with feedback as shown in
Figure 14.
CLKIN
Delay
1
Delay
2
Delay
n-1
Delay
n
CLK0
CLK90
CLK180
CLK270
CLK2X
CLK2X180
CLKDV
Control
LOCKED
CLKFB
RST
Phase
Detection
DS099-2_08_041103
Figure 14: Simplified Functional Diagram of DLL
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DS099-2 (v1.2) July 11, 2003
1-800-255-7778
Advance Product Specification
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