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R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 19: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard
Add the
Adjustment
Below
Speed Grade
-5
-4
Units
LVCMOS33
Slow 2 mA 6.22 6.22
ns
4 mA 3.80 3.80
ns
6 mA 3.02 3.02
ns
8 mA 3.04 3.04
ns
12 mA 2.18 2.18
ns
16 mA 2.05 2.05
ns
24 mA 1.82 1.82
ns
Fast 2 mA 3.15 3.15
ns
4 mA 1.30 1.30
ns
6 mA 0.53 0.53
ns
8 mA 0.54 0.54
ns
12 mA 0.14 0.14
ns
16 mA 0.08 0.08
ns
24 mA –0.03 –0.03 ns
LVDCI_33
0
0
ns
LVDCI_DV2_33
0
0
ns
LVTTL
Slow 2 mA 6.24 6.24
ns
4 mA 3.81 3.81
ns
6 mA 3.03 3.03
ns
8 mA 3.02 3.02
ns
12 mA 2.17 2.17
ns
16 mA 2.05 2.05
ns
24 mA 1.88 1.88
ns
Fast 2 mA 3.14 3.14
ns
4 mA 1.31 1.31
ns
6 mA 0.50 0.50
ns
8 mA 0.51 0.51
ns
12 mA 0.12 0.12
ns
16 mA 0.06 0.06
ns
24 mA
0
0
ns
Table 19: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard
Add the
Adjustment
Below
Speed Grade
-5
-4
Units
PCI33_3
–0.26 –0.26 ns
SSTL18_I
–0.05 –0.05 ns
SSTL18_I_DCI
–0.01 –0.01 ns
SSTL2_I
0.08 0.08
ns
SSTL2_I_DCI
0.01 0.01
ns
SSTL2_II
–0.04 –0.04 ns
SSTL2_II_DCI
–0.14 –0.14 ns
Differential Standards
LDT_25
–0.52 –0.52 ns
LVDS_25
–0.50 –0.50 ns
LVDS_25_DCI
ns
BLVDS_25
–0.01 –0.01 ns
LVDSEXT_25
–0.50 –0.50 ns
LVDSEXT_25_DCI
ns
ULVDS_25
–0.48 –0.48 ns
LVPECL_25
ns
RSDS_25
ns
Notes:
1. The numbers in this table are tested using the methodology
presented in Table 20 and are based on the operating
conditions set forth in Table 5, Table 8, and Table 10.
2. These adjustments are used to convert output- and
three-state-path times originally specified for the LVCMOS25
standard with 12 mA drive and Fast slew rate to times that
correspond to other signal standards. Do not adjust times
that measure when outputs go into a high-impedance state.
DS099-3 (v1.3) March 4, 2004
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