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Spartan-3 FPGA Family: Pinout Descriptions
PQ208: 208-lead Plastic Quad Flat Pack
The 208-lead plastic quad flat package, PQ208, supports
three different Spartan-3 devices, including the XC3S50,
the XC3S200, and the XC3S400. The footprints for the
XC3S200 and XC3S400 are identical, as shown in Table 20
and Figure 10. The XC3S50, however, has fewer I/O pins
resulting in 17 unconnected pins on the PQ208 package,
labeled as “N.C.” In Table 20 and Figure 10, these uncon-
nected pins are indicated with a black diamond symbol (‹).
All the package pins appear in Table 20 and are sorted by
bank number, then by pin name. Pairs of pins that form a dif-
ferential I/O pair appear together in the table. The table also
shows the pin number for each pin and the pin type, as
defined earlier.
If there is a difference between the XC3S50 pinout and the
pinout for the XC3S200 and XC3S400, then that difference
is highlighted in Table 20. If the table entry is shaded grey,
then there is an unconnected pin on the XC3S50 that maps
to a user-I/O pin on the XC3S200 and XC3S400. If the table
entry is shaded tan, then the unconnected pin on the
XC3S50 maps to a VREF-type pin on the XC3S200 and
XC3S400. If the other VREF pins in the bank all connect to
a voltage reference to support a special I/O standard, then
also connect the N.C. pin on the XC3S50 to the same VREF
voltage. This provides maximum flexibility as you could
potentially migrate a design from the XC3S50 device to an
XC3S200 or XC3S400 FPGA without changing the printed
circuit board.
Pinout Table
Table 20: PQ208 Package Pinout
Bank
XC3S50
Pin Name
XC3S200
XC3S400
Pin Name
0
IO
IO
0
IO
0
N.C. (‹)
IO
IO/VREF_0
0
IO/VREF_0 IO/VREF_0
0
IO_L01N_0/ IO_L01N_0/
VRP_0
VRP_0
0
IO_L01P_0/ IO_L01P_0/
VRN_0
VRN_0
0
IO_L25N_0 IO_L25N_0
0
IO_L25P_0 IO_L25P_0
0
IO_L27N_0 IO_L27N_0
0
IO_L27P_0 IO_L27P_0
0
IO_L30N_0 IO_L30N_0
0
IO_L30P_0 IO_L30P_0
0
IO_L31N_0 IO_L31N_0
0
IO_L31P_0/ IO_L31P_0/
VREF_0
VREF_0
PQ208
Pin
Number
P189
P197
P200
P205
P204
P203
P199
P198
P196
P194
P191
P190
P187
P185
Type
I/O
I/O
VREF
VREF
DCI
DCI
I/O
I/O
I/O
I/O
I/O
I/O
I/O
VREF
Table 20: PQ208 Package Pinout (Continued)
Bank
XC3S50
Pin Name
XC3S200
XC3S400
Pin Name
PQ208
Pin
Number
Type
0
IO_L32N_0/ IO_L32N_0/
P184
GCLK
GCLK7
GCLK7
0
IO_L32P_0/ IO_L32P_0/
P183
GCLK
GCLK6
GCLK6
0
VCCO_0
VCCO_0
P188 VCCO
0
VCCO_0
VCCO_0
P201 VCCO
1
IO
IO
P167
I/O
1
IO
IO
P175
I/O
1
IO
IO
P182
I/O
1
IO_L01N_1/ IO_L01N_1/
P162
DCI
VRP_1
VRP_1
1
IO_L01P_1/ IO_L01P_1/
P161
DCI
VRN_1
VRN_1
1
IO_L10N_1/ IO_L10N_1/
P166
VREF
VREF_1
VREF_1
1
IO_L10P_1 IO_L10P_1
P165
I/O
1
IO_L27N_1 IO_L27N_1
P169
I/O
1
IO_L27P_1 IO_L27P_1
P168
I/O
1
IO_L28N_1 IO_L28N_1
P172
I/O
1
IO_L28P_1 IO_L28P_1
P171
I/O
1
IO_L31N_1/ IO_L31N_1/
P178
VREF
VREF_1
VREF_1
1
IO_L31P_1 IO_L31P_1
P176
I/O
1
IO_L32N_1/ IO_L32N_1/
P181
GCLK
GCLK5
GCLK5
1
IO_L32P_1/ IO_L32P_1/
P180
GCLK
GCLK4
GCLK4
1
VCCO_1
VCCO_1
P164 VCCO
1
VCCO_1
2
N.C. (‹)
VCCO_1
IO/VREF_2
P177
P154
VCCO
VREF
2
IO_L01N_2/ IO_L01N_2/
P156
DCI
VRP_2
VRP_2
2
IO_L01P_2/ IO_L01P_2/
P155
DCI
VRN_2
VRN_2
2
IO_L19N_2 IO_L19N_2
P152
I/O
2
IO_L19P_2 IO_L19P_2
P150
I/O
2
IO_L20N_2 IO_L20N_2
P149
I/O
2
IO_L20P_2 IO_L20P_2
P148
I/O
2
IO_L21N_2 IO_L21N_2
P147
I/O
2
IO_L21P_2 IO_L21P_2
P146
I/O
2
IO_L22N_2 IO_L22N_2
P144
I/O
2
IO_L22P_2 IO_L22P_2
P143
I/O
2
IO_L23N_2/ IO_L23N_2/
P141
VREF
VREF_2
VREF_2
2
IO_L23P_2 IO_L23P_2
P140
I/O
DS099-4 (v1.5) July 13, 2004
www.xilinx.com
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Product Specification
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