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Spartan-3 FPGA Family: DC and Switching Characteristics
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Table 19: Output Timing Adjustments for IOB
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard
Add the
Adjustment
Below
Speed Grade
-5
-4
Single-Ended Standards
GTL
–0.18 –0.18
GTL_DCI
–0.15 –0.15
GTLP
–0.15 –0.15
GTLP_DCI
–0.13 –0.13
HSTL_I
0.08 0.08
HSTL_I_DCI
0.07 0.07
HSTL_III
–0.05 –0.05
HSTL_III_DCI
–0.05 –0.05
HSTL_I_18
0.14 0.14
HSTL_I_DCI_18
0
0
HSTL_II_18
–0.13 –0.13
HSTL_II_DCI_18
0.31 0.31
HSTL_III_18
–0.02 –0.02
HSTL_III_DCI_18
–0.03 –0.03
LVCMOS12
Slow 2 mA 6.47 6.47
4 mA 6.70 6.70
6 mA 5.60 5.60
Fast 2 mA 3.04 3.04
4 mA 2.25 2.25
6 mA 2.10 2.10
LVCMOS15
Slow 2 mA 3.95 3.95
4 mA 3.49 3.49
6 mA 2.85 2.85
8 mA 3.44 3.44
12 mA 2.82 2.82
Fast 2 mA 2.29 2.29
4 mA 1.37 1.37
6 mA 1.15 1.15
8 mA 1.13 1.13
12 mA 1.00 1.00
LVDCI_15
1.34 1.34
LVDCI_DV2_15
1.14 1.14
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 19: Output Timing Adjustments for IOB (Continued)
Convert Output Time from
LVCMOS25 with 12mA Drive and
Fast Slew Rate to the Following
Signal Standard
Add the
Adjustment
Below
Speed Grade
-5
-4
Units
LVCMOS18
Slow 2 mA 4.31 4.31
ns
4 mA 2.69 2.69
ns
6 mA 2.23 2.23
ns
8 mA 1.83 1.83
ns
12 mA 1.97 1.97
ns
16 mA 1.62 1.62
ns
Fast 2 mA 2.07 2.07
ns
4 mA 0.90 0.90
ns
6 mA 0.77 0.77
ns
8 mA 0.61 0.61
ns
12 mA 0.56 0.56
ns
16 mA 0.50 0.50
ns
LVDCI_18
0.72 0.72
ns
LVDCI_DV2_18
0.58 0.58
ns
LVCMOS25
Slow 2 mA 5.11 5.11
ns
4 mA 3.17 3.17
ns
6 mA 2.53 2.53
ns
8 mA 2.21 2.21
ns
12 mA 1.79 1.79
ns
16 mA 1.77 1.77
ns
24 mA 1.53 1.53
ns
Fast 2 mA 2.30 2.30
ns
4 mA 0.87 0.87
ns
6 mA 0.30 0.30
ns
8 mA 0.21 0.21
ns
12 mA
0
0
ns
16 mA 0.11 0.11
ns
24 mA 0.04 0.04
ns
LVDCI_25
0.19 0.19
ns
LVDCI_DV2_25
0.10 0.10
ns
18
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DS099-3 (v1.3) March 4, 2004
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