XC3S50 Datasheet, PDF (12/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

R
Spartan-3 1.2V FPGA Family: Functional Description
output voltage swing for all standards except GTL and
GTLP.
All single-ended standards except the LVCMOS modes
require a Reference Voltage (V_REF) to bias the input-switch-
ing threshold. Once a configuration data file is loaded into
the FPGA that calls for the I/Os of a given bank to use such
a signal standard, a few specifically reserved I/O pins on the
same bank automatically convert to V_REF inputs. When
using one of the LVCMOS standards, these pins remain
I/Os because the V_CCO voltage biases the input-switching
threshold, so there is no need for V_REF. Select the V_CCO and
V_REF levels to suit the desired single-ended standard
according to Table 4.
Differential standards employ a pair of signals, one the
opposite polarity of the other. The noise canceling (e.g.,
Common-Mode Rejection) properties of these standards
permit exceptionally high data transfer rates. This section
introduces the differential signaling capabilities of Spartan-3
devices.
Each device-package combination designates specific I/O
pairs that are specially optimized to support differential
standards. A unique “L-number”, part of the pin name, iden-
tifies the line-pairs associated with each bank (see Module
4: Pinout Descriptions). For each pair, the letters “P” and
“N” designate the true and inverted lines, respectively. For
example, the pin names IO_L43P_7 and IO_L43N_7 indi-
cate the true and inverted lines comprising the line pair L43
on Bank 7. The differential Output Voltage (V_OD) parameter
measures the voltage difference the High and Low logic lev-
els that a pair of differential outputs drive. The V_OD range for
each of the differential standards is listed in Table 5. The
V_CCO lines provide current to the outputs. The V_REF lines
are not used. Select the V_CCO level to suit the desired differ-
ential standard according to Table 5.
Table 4: Single-Ended I/O Standards (Values in Volts)
Signal
Standard
GTL
V_CCO
For
For
Outputs Inputs
Note 2 Note 2
V_REF for
Inputs⁽¹⁾
0.8
Board
Termination
Voltage (V_TT)
1.2
GTLP
Note 2 Note 2
1
1.5
HSTL_I
1.5
-
0.75
0.75
HSTL_III
1.5
-
0.9
1.5
HSTL_I_18
1.8
-
0.9
0.9
HSTL_II_18
1.8
-
0.9
0.9
HSTL_III_18
1.8
-
1.1
1.8
LVCMOS12
1.2
1.2
-
-
LVCMOS15
1.5
1.5
-
-
LVCMOS18
1.8
1.8
-
-
LVCMOS25
2.5
2.5
-
-
LVCMOS33
3.3
3.3
-
-
LVTTL
3.3
3.3
-
-
Table 4: Single-Ended I/O Standards (Values in Volts)
Signal
Standard
PCI33_3
V_CCO
For
For
Outputs Inputs
3.0
3.0
V_REF for
Inputs⁽¹⁾
-
Board
Termination
Voltage (V_TT)
-
SSTL18_I
1.8
-
0.9
0.9
SSTL2_I
2.5
-
1.25
1.25
SSTL2_II
2.5
-
1.25
1.25
Notes:
1. Banks 4 and 5 of any Spartan-3 device in a VQ100 package
do not support signal standards using V_REF.
2. The V_CCO level used for the GTL and GTLP standards must
be no lower than the termination voltage (V_TT), nor can it be
lower than the voltage at the I/O pad.
3. See Table 6 for a listing of the single-ended DCI standards.
Table 5: Differential I/O Standards
Signal
Standard
V_CCO (Volts)
For
For
Outputs Inputs
V_REF for
Inputs
(Volts)
V_OD(1) (mV)
Min. Max.
LDT_25
2.5
-
-
430 670
LVDS_25
2.5
-
-
250 400
BLVDS_25
2.5
-
-
250 450
LVDSEXT_25 2.5
-
-
330 700
ULVDS_25
2.5
-
-
430 670
RSDS_25
2.5
-
-
100 400
Notes:
1. Measured with a termination resistor value (RT) of 100
Ohms.
2. See Table 6 for a listing of the differential DCI standards.
The need to supply V_REF and V_CCO imposes constraints on
which standards can be used in the same bank. See The
Organization of IOBs into Banks section for additional
guidelines concerning the use of the V_CCO and V_REF lines.
Digitally Controlled Impedance (DCI)
When the round-trip delay of an output signal — i.e., from
output to input and back again — exceeds rise and fall
times, it is common practice to add termination resistors to
the line carrying the signal. These resistors effectively
match the impedance of a device’s I/O to the characteristic
impedance of the transmission line, thereby preventing
reflections that adversely affect signal integrity. However,
with the high I/O counts supported by modern devices, add-
ing resistors requires significantly more components and
board area. Furthermore, for some packages — e.g., ball
grid arrays — it may not always be possible to place resis-
tors close to pins.
DCI answers these concerns by providing two kinds of
on-chip terminations: Parallel terminations make use of an
integrated resistor network. Series terminations result from
controlling the impedance of output drivers. DCI actively
adjusts both parallel and series terminations to accurately
DS099-2 (v1.2) July 11, 2003
www.xilinx.com
5
Advance Product Specification
1-800-255-7778