XC3S50 Datasheet, PDF (79/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: DC and Switching Characteristics
R
Phase Shifter (PS)
Phase Shifter operation is only supported in the Low fre-
quency mode. For Rev. 0 devices, the Variable Phase mode
only permits positive shifts. For any desired negative phase
shift (–S), an equivalent positive phase shift (360° – S) is
possible. In order to use the Variable Phase mode, it is nec-
essary to set the BitGen option Centered_x#y# option to 0.
BitGen is part of the Xilinx development software. The lines
to be typed in the command prompt are shown in Table 33,
page 33.
Table 31: Recommended Operating Conditions for the PS in Variable Phase Mode
Speed Grade
Symbol
Description
Operating Frequency Ranges
Frequency Mode/
F_PSCLK Range
Device
Revision
-5
Min
Max
-4
Min
Max
PSCLK_FREQ Frequency for the
Low
(F_PSCLK)
PSCLK input
Input Pulse and Requirements
All
1
165
1
165
PSCLK_PULSE PSCLK pulse width
as a percentage of
the PSCLK period
Low
Low F_PSCLK < 200 MHz
F_PSCLK > 200 MHz
0
Future
45%
40%
45%
55%
60%
55%
Notes:
1. The PS specifications in this table apply when the PS attribute CLKOUT_PHASE_SHIFT= VARIABLE.
45%
40%
45%
55%
60%
55%
Units
MHz
-
-
-
Table 32: Switching Characteristics for the PS in Variable Phase Mode
Speed Grade
Symbol
Description
Frequency
Mode
-5
Min
Max
-4
Min
Max
Units
Phase Shifting Range
FINE_SHIFT_RANGE
Range for variable
Low
phase shifting
-
10.0
-
10.0
ns
Lock Time
LOCK_DLL_FINE_SHIFT⁽³⁾ In the Variable
Low
-
Phase mode, the
additional time it
takes for the DCM’s
LOCKED output to
go High
-
ms
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 5 and Table 31.
2. The PS specifications in this table apply when the PS attribute CLKOUT_PHASE_SHIFT= VARIABLE.
3. When in the Variable Phase mode, add the values for this parameter to the appropriate LOCK_DLL parameter from Table 28 for the
total lock time.
32
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