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Spartan-3 FPGA Family: Pinout Descriptions
R
Configuration Data Byte
0xA5 =
I/O Bank 4 (VCCO_4)
High Nibble
D0
D1
D2
D3
1
0
1
0
I/O Bank 5 (VCCO_5)
Low Nibble
D4
D5
D6
D7
0
1
0
1
Figure 2: Configuration Data Byte Mapping to D0-D7 Bits
Parallel Configuration Modes (SelectMAP)
This section describes the dual-purpose configuration pins
used during the Master and Slave Parallel configuration
modes, sometimes also called the SelectMAP modes. In
both Master and Slave Parallel configuration modes, D0-D7
form the byte-wide configuration data input. See Table 7 for
Mode Select pin settings required for Parallel modes.
As shown in Figure 2, D0 is the most-significant bit while D7
is the least-significant bit. Bits D0-D3 form the high nibble of
the byte and bits D4-D7 form the low nibble.
In the Parallel configuration modes, both the VCCO_4 and
VCCO_5 voltage supplies are required and must both equal
the voltage of the attached configuration device, typically
either 2.5V or 3.3V.
Assert Low both the chip-select pin, CS_B, and the
read/write control pin, RDWR_B, to write the configuration
data byte presented on the D0-D7 pins to the FPGA on a
rising-edge of the configuration clock, CCLK. The order of
CS_B and RDWR_B does not matter, although RDWR_B
must be asserted throughout the configuration process. If
RDWR_B is de-asserted during configuration, the FPGA
aborts the configuration operation.
After configuration, these pins are available as general-pur-
pose user I/O. However, the SelectMAP configuration inter-
face is optionally available for debugging and dynamic
reconfiguration. To use these SelectMAP pins after configu-
ration, set the Persist bitstream generation option.
The Readback debugging option, for example, requires the
Persist bitstream generation option. During Readback
mode, assert CS_B Low, along with RDWR_B High, to read
a configuration data byte from the FPGA to the D0-D7 bus
on a rising CCLK edge. During Readback mode, D0-D7 are
output pins.
In all the cases, the configuration data and control signals
are synchronized to the rising edge of the CCLK clock sig-
nal.
8
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