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Spartan-3 FPGA Family: DC and Switching Characteristics
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Table 28: Switching Characteristics for the DLL (Continued)
Speed Grade
Symbol
Phase Alignment
Description
Frequency Mode /
F_CLKIN Range
Device
Revision
-5
-4
Min Max Min Max Units
CLKIN_CLKFB_PHASE
Phase offset
All
between the
CLKIN and CLKFB
inputs
All
-50 +50 -50 +50 ps
CLKOUT_PHASE
Phase offset
All
between any DLL
output and any
other DCM outputs
All
-140 +140 -140 +140 ps
Lock Time
LOCK_DLL_24_30
LOCK_DLL_30_40
LOCK_DLL_40_50
LOCK_DLL_50_60
LOCK_DLL_60
Delay Lines
Time required to 24 MHz < F_CLKIN < 30 MHz
All
achieve lock
30 MHz < F_CLKIN < 40 MHz
40 MHz < F_CLKIN < 50 MHz
50 MHz < F_CLKIN < 60 MHz
F_CLKIN > 60 MHz
- 960 - 960 µs
- 720 - 720 µs
- 400 - 400 µs
- 200 - 200 µs
- 160 - 160 µs
DCM_TAP
Delay tap
resolution
All
All
30.0 60.0 30.0 60.0 ps
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 5 and Table 27.
2. DLL specifications apply when any of the DLL outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, or CLKDV) are in use.
3. For Rev. 0 devices only, use feedback from the CLK0 output (instead of the CLK2X output) and set the CLK_FEEDBACK attribute to
1X.
4. This specification only applies if the attribute DUTY_CYCLE_CORRECTION = TRUE.
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