XC3S50 Datasheet, PDF (191/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: Pinout Descriptions
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Revision History
Date
04/03/03
04/21/03
05/12/03
07/11/03
07/29/03
08/19/03
10/09/03
12/17/03
02/27/04
07/13/04
Version No.
Description
1.0
Initial Xilinx release.
1.1
Added information on the VQ100 package footprint, including a complete pinout table
(Table 16) and footprint diagram (Figure 8).
Updated Table 15 with final I/O counts for the VQ100 package. Also added final differential I/O
pair counts for the TQ144 package.
Added clarifying comments to HSWAP_EN pin description on page 13.
Updated the footprint diagram for the FG900 package shown in Figure 15a and Figure 15b.
Some thick lines separating I/O banks were incorrect.
Made cosmetic changes to Figure 1, Figure 3, and Figure 4.
Updated Xilinx hypertext links.
Added XC3S200 and XC3S400 to Pin Name column in Table 18.
1.1.1
AM32 pin was missing GND label in FG1156 package diagram (Figure 16).
1.1.2
Corrected misspellings of GCLK in Table 1 and Table 2. Changed CMOS25 to LVCMOS25 in
Dual-Purpose Pin I/O Standard During Configuration section. Clarified references to
Module 2. For XC3S5000 in FG1156 package, corrected N.C. symbol to a black square in
Table 37, key, and package drawing.
1.2
Corrected pin names on FG1156 package. Some package balls incorrectly included LVDS pair
names. The affected balls on the FG1156 package include G1, G2, G33, G34, U9, U10, U25,
U26, V9, V10, V25, V26, AH1, AH2, AH33, AH34. The number of LVDS pairs is unaffected.
Modified affected balls and re-sorted rows in Table 37. Updated affected balls in Figure 16.
Also updated ASCII and Excel electronic versions of FG1156 pinout.
1.2.1
Removed 100 MHz ConfigRate option in CCLK: Configuration Clock section and in Table 11.
Added note that TDO is a totem-pole output in Table 9.
1.2.2
Some pins had incorrect bank designations and were improperly sorted in Table 20. No pin
names or functions changed. Renamed DCI_IN to DCI and added black diamond to N.C. pins
in Table 20. In Figure 10, removed some extraneous text from pin 106 and corrected spelling
of pins 45, 48, and 81.
1.3
Added FG320 pin tables and pinout diagram (FG320: 320-lead Fine-pitch Ball Grid Array).
Made cosmetic changes to the TQ144 footprint (Figure 9), the PQ208 footprint (Figure 10), the
FG676 footprint (Figure 14), and the FG900 footprint (Figure 15). Clarified wording in
Precautions When Using the JTAG Port in 3.3V Environments section.
1.4
Clarified wording in Using JTAG Port After Configuration section. In Table 12, reduced
package height for FG320 and increased maximum I/O values for the FG676, FG900, and
FG1156 packages.
1.5
Added information on lead-free (Pb-free) package options to the Package Overview section
plus Table 12 and Table 13. Clarified the VRN_# reference resistor requirements for I/O
standards that use single termination as described in the DCI Termination Types section and
in Figure 3b. Graduated from Advance Product Specification to Product Specification.
104
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