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R
Spartan-3 FPGA Family: DC and Switching Characteristics
Table 29: Recommended Operating Conditions for the DFS
Speed Grade
Symbol
Input Frequency Ranges⁽²⁾
Description
Frequency
Mode
-5
Min
Max
-4
Min
Max
Units
F_CLKIN
CLK_FREQ_FX
Frequency for the
CLK_FREQ_FX_HF ^{CLKIN input}
Low
High
1
210
1
210 MHz
48
280
48
280 MHz
Input Clock Jitter
CLKIN_CYC_JITT_FX_LF
CLKIN_CYC_JITT_FX_HF
Cycle-to-cycle jitter at
the CLKIN input
Low
High
-300 +300 -300 +300 ps
-150 +150 -150 +150 ps
CLKIN_CYC_PER_FX_LF
CLKIN_CYC_PER_FX_HF
Period jitter at the
CLKIN input
Low
High
-1
+1
-1
+1
ns
-1
+1
-1
+1
ns
Notes:
1. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) are in use.
2. If both DFS and DLL outputs are used on the same DCM, follow the more restrictive CLKIN_FREQ_DLL specifications in Table 27.
Table 30: Switching Characteristics for the DFS
Speed Grade
Symbol
Description
Frequency Device
Mode Revision
-5
Min
Max
-4
Min Max
Output Frequency Ranges
CLKOUT_FREQ_FX_LF
Frequency for the CLKFX
Low
All
24
210
24
210
CLKOUT_FREQ_FX_HF
and CLKFX180 outputs
High
0
210
280 210 280
Future
210
326 210 TBD
Output Clock Jitter
CLKOUT_PER_JITT_FX
Period jitter at the CLKFX
All
All
and CLKFX180 outputs
Duty Cycle⁽³⁾
CLKOUT_DUTY_CYCLE_FX Duty cycle precision for
All
the CLKFX and
CLKFX180 outputs
All
-100
+100 -100 +100
Phase Alignment
CLKOUT_PHASE
Phase offset between
All
either DFS output and
any other DCM output
All
-140
+140 -140 +140
Lock Time
LOCK_FX
Once the CLKIN and
All
All
CLKFB signals become
in-phase, the time it takes
for the DCM’s LOCKED
output to go High.
-
10.0
-
10.0
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 5 and Table 29.
2. DFS specifications apply when either of the DFS outputs (CLKFX or CLKFX180) is in use.
3. The CLKFX and CLKFX180 outputs always approximate 50% duty cycles.
Units
MHz
MHz
MHz
ps
ps
ps
ms
DS099-3 (v1.3) March 4, 2004
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