XC3S50 Datasheet, PDF (121/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: Pinout Descriptions
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Table 20: PQ208 Package Pinout (Continued)
Bank
XC3S50
Pin Name
XC3S200
XC3S400
Pin Name
PQ208
Pin
Number
Type
N/A VCCAUX
VCCAUX
P142 VCCAUX
N/A VCCAUX
VCCAUX
P121 VCCAUX
N/A VCCAUX
VCCAUX
P89 VCCAUX
N/A VCCAUX
VCCAUX
P69 VCCAUX
N/A VCCAUX
VCCAUX
P38 VCCAUX
N/A VCCAUX
VCCAUX
P17 VCCAUX
N/A VCCINT
VCCINT
P192 VCCINT
N/A VCCINT
VCCINT
P174 VCCINT
N/A VCCINT
VCCINT
P88 VCCINT
N/A VCCINT
VCCINT
P70 VCCINT
VCCAUX CCLK
CCLK
P104 CONFIG
VCCAUX DONE
DONE
P103 CONFIG
VCCAUX HSWAP_EN HSWAP_EN P206 CONFIG
VCCAUX M0
M0
P55 CONFIG
Table 20: PQ208 Package Pinout (Continued)
Bank
XC3S50
Pin Name
XC3S200
XC3S400
Pin Name
PQ208
Pin
Number
Type
VCCAUX M1
M1
P54 CONFIG
VCCAUX M2
M2
P56 CONFIG
VCCAUX PROG_B
PROG_B
P207 CONFIG
VCCAUX TCK
TCK
P159
JTAG
VCCAUX TDI
TDI
P208
JTAG
VCCAUX TDO
TDO
P158
JTAG
VCCAUX TMS
TMS
P160
JTAG
User I/Os by Bank
Table 21 indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks for the XC3S50 in the
PQ208 package. Similarly, Table 22 shows how the avail-
able user-I/O pins are distributed between the eight I/O
banks for the XC3S200 and XC3S400 in the PQ208 pack-
age.
Table 21: User I/Os Per Bank for XC3S50 in PQ208 Package
Maximum
Package Edge I/O Bank
I/O
I/O
All Possible I/O Pins by Type
DUAL
DCI
VREF
0
15
9
0
2
2
Top
1
15
9
0
2
2
2
16
13
0
2
2
Right
3
16
12
0
2
2
4
15
3
6
2
2
Bottom
5
15
3
6
2
2
6
16
12
0
2
2
Left
7
16
12
0
2
2
GCLK
2
2
0
0
2
2
0
0
34
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