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| XC3S50 Datasheet, PDF (14/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology | |||
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R
Table 7: DCI Terminations
Termination
Controlled impedance output driver
Spartan-3 1.2V FPGA Family: Functional Description
Schematic(1)
IOB
R
Z0
I/O Standards
LVDCI_15
LVDCI_18
LVDCI_25
LVDCI_33
Controlled output driver with half impedance
IOB
R/2
Z0
LVDCI_DV2_15
LVDCI_DV2_18
LVDCI_DV2_25
LVDCI_DV2_33
Single resistor
IOB
VCCO
GTL_DCI
GTLP_DCI
HSTL_III_DCI(2)
R
Z0
HSTL_III_DCI_18(2)
Split resistors
IOB
VCCO
HSTL_I_DCI(2)
HSTL_I_DCI_18(2)
HSTL_II_DCI_18
2R Z0
LVDS_25_DCI
LVDSEXT_25_DCI
2R
Split resistors with output driver impedance
fixed to 25â¦
IOB
25â¦
VCCO
2R Z0
2R
SSTL18_I_DCI(3)
SSTL2_I_DCI(3)
SSTL2_II_DCI
Notes:
1. The value of R is equivalent to the characteristic impedance of the line connected to the I/O. It is also equal to half the value of RREF
for the DV2 standards and RREF for all other DCI standards.
2. For DCI using HSTL Classes I and III, terminations only go into effect at inputs (not at outputs).
3. For DCI using SSTL Class I, the split termination only goes into effect at inputs (not at outputs).
DS099-2 (v1.2) July 11, 2003
www.xilinx.com
7
Advance Product Specification
1-800-255-7778
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