XC3S50 Datasheet, PDF (81/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 FPGA Family: DC and Switching Characteristics
R
Configuration and JTAG Timing
V_CCINT
1.2V
(Supply)
V_CCAUX
2.5V
(Supply)
V_CCO Bank 4
2.5V
(Supply)
PROG_B
(Input)
INIT_B
(Open-Drain)
CCLK
(Output)
T_POR
T_PROG
T_PL
T_ICCK
DS099-3_03_022904
Notes:
1. The V_CCINT, V_CCAUX, and V_CCO supplies may be applied in any order.
2. The Low-going pulse on PROG_B is optional after power-on but necessary for reconfiguration without a power cycle.
3. The rising edge of INIT_B samples the voltage levels applied to the mode pins (M0 - M2).
Figure 5: Waveforms for Power-On and the Beginning of Configuration
Table 34: Power-On Timing and the Beginning of Configuration
Symbol
T_POR(2)
Description
The time from the application of V_CCINT, V_CCAUX, and
V_CCO Bank 4 supply voltages (whichever occurs last)
to the rising transition of the INIT_B pin
Device
XC3S50
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
XC3S5000
T_PROG
T_PL(2)
The width of the low-going pulse on the PROG_B pin All
The time from the rising edge of the PROG_B pin to XC3S50
the rising transition on the INIT_B pin
XC3S200
XC3S400
XC3S1000
XC3S1500
XC3S2000
XC3S4000
T_ICCK(3)
The time from the rising edge of the INIT_B pin to the
generation of the configuration clock signal at the
CCLK output pin
XC3S5000
All
Notes:
1. The numbers in this table are based on the operating conditions set forth in Table 5.
2. Power-on reset and the clearing of configuration memory occurs during this period.
3. This specification applies only for the Master Serial and Master Parallel modes.
All Speed Grades
Min
Max
-
5
-
5
-
5
-
5
-
7
-
7
-
7
-
7
0.3
-
-
2
-
2
-
2
-
2
-
3
-
3
-
3
-
3
0.5
4.0
Units
ms
ms
ms
ms
ms
ms
ms
ms
µs
ms
ms
ms
ms
ms
ms
ms
ms
µs
34
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DS099-3 (v1.3) March 4, 2004
1-800-255-7778
Advance Product Specification