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Spartan-3 FPGA Family: Pinout Descriptions
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Table 10: Pin Behavior After Power-Up, During Configuration (Continued)
Configuration Mode Settings <M2:M1:M0>
Pin Name
Serial Modes
Master
<0:0:0>
Slave
<1:1:1>
SelectMap Parallel Modes
Master
<0:1:1>
Slave
<1:1:0>
JTAG Mode
<1:0:1>
Bitstream
Configuration
Option
VCCINT: Internal core voltage supply pins
VCCINT
+1.2V
+1.2V
+1.2V
+1.2V
+1.2V
GND: Ground supply pins
GND
GND
GND
GND
GND
GND
Notes:
1. #= I/O bank number, an integer from 0 to 7.
2. (I) = input, (O) = output, (OD) = open-drain output, (I/O) = bidirectional, (I/OD) = bidirectional with open-drain output. Open-drain
output requires pull-up to create logic High level.
3.
Shaded cell indicates that the pin is high-impedance during configuration. To enable a soft pull-up resistor during configuration,
drive or tie HSWAP_EN Low.
Bitstream Options
Table 11 lists the various bitstream options that affect pins
on a Spartan-3 FPGA. The table shows the names of the
affected pins, describes the function of the bitstream option,
the name of the bitstream generator option variable, and the
legal values for each variable. The default option setting for
each variable is indicated with bold, underlined text.
Table 11: Bitstream Options Affecting Spartan-3 Pins
Affected Pin
Name(s)
Bitstream Generation Function
All unused I/O pins of
type I/O, DUAL,
GCLK, DCI, VREF
For all I/O pins that are unused after configuration, this option
defines whether the I/Os are individually tied to VCCO via a weak
pull-up resistor, tied ground via a weak pull-down resistor, or left
floating. If left floating, the unused pins should be connected to a
defined logic level, either from a source internal to the FPGA or
external.
IO_Lxxy_#/DIN,
IO_Lxxy_#/DOUT,
IO_Lxxy_#/INIT_B
Serial configuration mode: If set to Yes, then these pins retain their
functionality after configuration completes, allowing for device
(re-)configuration. Readback is not supported in with serial mode.
IO_Lxxy_#/D0,
IO_Lxxy_#/D1,
IO_Lxxy_#/D2,
IO_Lxxy_#/D3,
IO_Lxxy_#/D4,
IO_Lxxy_#/D5,
IO_Lxxy_#/D6,
IO_Lxxy_#/D7,
IO_Lxxy_#/CS_B,
IO_Lxxy_#/RDWR_B,
IO_Lxxy_#/BUSY,
IO_Lxxy_#/INIT_B
Parallel configuration mode (also called SelectMAP): If set to Yes,
then these pins retain their SelectMAP functionality after
configuration completes, allowing for device readback and for
partial or complete (re-)configuration.
CCLK
After configuration, this bitstream option either pulls CCLK to
VCCAUX via a weak pull-up resistor, or allows CCLK to float.
CCLK
For Master configuration modes, this option sets the approximate
frequency, in MHz, for the internal silicon oscillator.
Option
Variable
Name
Values
(default
value)
UnusedPin ^{• Pulldown}
• Pullup
• Pullnone
Persist
• No
• Yes
Persist
• No
• Yes
CclkPin ^{• Pullup}
• Pullnone
ConfigRate 3, 6, 12, 25,
50
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