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XC3S50 Datasheet, PDF (52/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology
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Spartan-3 FPGA Family: DC and Switching Characteristics
Table 8: Recommended Operating Conditions for User I/Os Using Single-Ended Standards
Signal Standard
GTL(2)
GTL_DCI
GTLP(2)
GTLP_DCI
HSTL_I, HSTL_I_DCI
HSTL_III,
HSTL_III_DCI
Min (V)
-
-
-
-
1.4
1.4
VCCO
Nom (V)
-
1.2
-
1.5
1.5
1.5
Max (V)
-
-
-
-
1.6
1.6
Min (V)
0.74
0.74
0.88
0.88
0.68
0.68
VREF
Nom (V)
0.8
0.8
1
1
0.75
0.9
Max (V)
0.86
0.86
1.12
1.12
0.9
0.9
VIL
Max (V)
VREF - 0.05
VREF - 0.05
VREF - 0.1
VREF - 0.1
VREF - 0.1
VREF - 0.1
VIH
Min (V)
VREF + 0.05
VREF + 0.05
VREF + 0.1
VREF + 0.1
VREF + 0.1
VREF + 0.1
HSTL_I_18,
HSTL_I_DCI_18
1.7
1.8
1.9
-
0.9
-
VREF - 0.1
VREF + 0.1
HSTL_II_18,
HSTL_II_DCI_18
1.7
1.8
1.9
-
0.9
-
VREF - 0.1
VREF + 0.1
HSTL_III_18,
HSTL_III_DCI_18
1.7
1.8
1.9
-
1.1
-
VREF - 0.1
VREF + 0.1
LVCMOS12(3)
1.14
1.2
1.3
-
-
-
0.20VCCO
0.70VCCO
LVCMOS15,
LVDCI_15,
1.4
1.5
1.6
-
-
-
0.20VCCO
0.70VCCO
LVDCI_DV2_15(3)
LVCMOS18,
LVDCI_18,
1.7
1.8
1.9
-
-
-
0.20VCCO
0.70VCCO
LVDCI_DV2_18(3)
LVCMOS25(4),
LVDCI_25,
2.3
2.5
2.7
-
-
-
0.7
1.7
LVDCI_DV2_25(3)
LVCMOS33,
LVDCI_33,
3.0
3.3
3.45
-
-
-
0.8
2.0
LVDCI_DV2_33(3)
LVTTL
3.0
3.3
3.45
-
-
-
0.8
2.0
PCI33_3
SSTL18_I,
SSTL18_I_DCI
-
3.0
-
-
-
-
0.30VCCO
0.50VCCO
1.65
1.8
1.95
0.825
0.9
0.975
VREF - 0.125 VREF + 0.125
SSTL2_I,
SSTL2_I_DCI
2.3
2.5
2.7
1.15
1.25
1.35
VREF - 0.15
VREF + 0.15
SSTL2_II,
SSTL2_II_DCI
2.3
2.5
2.7
1.15
1.25
1.35
VREF - 0.15
VREF + 0.15
Notes:
1. Descriptions of the symbols used in this table are as follows:
VCCO -- the supply voltage for output drivers as well as LVCMOS, LVTTL, and PCI inputs
VREF -- the reference voltage for setting the input switching threshold
VIL -- the input voltage that indicates a Low logic level
VIH -- the input voltage that indicates a High logic level
2. Because the GTL and GTLP standards employ open-drain output buffers, VCCO lines do not supply current to the I/O circuit, rather
this current is provided using an external pull-up resistor connected from the I/O pin to a termination voltage (VTT). Nevertheless, the
voltage applied to the associated VCCO lines must always be at or above VTT and I/O pad voltages.
3. There is approximately 100 mV of hysteresis on inputs using any LVCMOS standard.
4. All Dedicated pins (M0-M2, CCLK, PROG_B, DONE, HSWAP_EN, TCK, TDI, TDO, and TMS) use the LVCMOS25 standard and draw
power from the VCCAUX rail (2.5V). The Dual-Purpose configuration pins (DIN/D0, D1-D7, CS_B, RDWR_B, BUSY/DOUT, and
INIT_B) use the LVCMOS25 standard before the User mode. For these pins, apply 2.5V to the VCCO Bank 4 and VCCO Bank 5 rails
at power-on as well as throughout configuration. For information concerning the use of 3.3V signals, see the 3.3V-Tolerant
Configuration Interface section in Module 2: Functional Description.
5. The global clock inputs have the following bank associations: GCLK0 and GCLK1 with Bank 4, GCLK2 and GCLK3 with Bank 5,
GCLK4 and GCLK5 with Bank 1, and GCLK6 and GCLK7 with Bank 0. The signal standards assigned to the Global Clock Lines (and
I/Os) of a given bank determine the VCCO voltage for that bank.
DS099-3 (v1.3) March 4, 2004
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