XC3S50 Datasheet, PDF (23/192 Pages) Xilinx, Inc – Revolutionary 90-nanometer process technology

Spartan-3 1.2V FPGA Family: Functional Description
R
“wide” words to form “narrow” words. When the data bus
width is eight bits or greater, extra parity bits become avail-
able. The width of the total data path (w) is the sum of the
DI/DO bus width and any parity bits (p).
The width selection made for the DI/DO bus determines the
number of address lines according to the relationship
expressed below:
r = 14 – [log(w–p)/log(2)]
(1)
In turn, the number of address lines delimits the total num-
ber (n) of addressable locations or depth according to the
following equation:
n = 2^r
(2)
The product of w and n yields the total block RAM capacity.
Equations (1) and (2) show that as the data bus width
increases, the number of address lines along with the num-
ber of addressable memory locations decreases. Using the
permissible DI/DO bus widths as inputs to these equations
provides the bus width and memory capacity measures
shown in Table 10.
Table 10: Port Aspect Ratios for Port A or B
DI/DO Bus Width
(w – p bits)
1
2
4
8
16
32
DIP/DOP
Bus Width (p bits)
0
0
0
1
2
4
Total Data Path
Width (w bits)
1
2
4
9
18
36
ADDR Bus
Width (r bits)
14
13
12
11
10
9
No. of
Addressable
Locations (n)
16,384
8,192
4,096
2,048
1,024
512
Block RAM
Capacity
(bits)
16,384
16,384
16,384
18,432
18,432
18,432
Block RAM Data Operations
Writing data to and accessing data from the block RAM are
synchronous operations that take place independently on
each of the two ports.
The waveforms for the write operation are shown in the top
half of the Figure 9, Figure 10, and Figure 11. When the WE
and EN signals enable the active edge of CLK, data at the
DI input bus is written to the block RAM location addressed
by the ADDR lines.
There are a number of different conditions under which data
can be accessed at the DO outputs. Basic data access
always occurs when the WE input is inactive. Under this
condition, data stored in the memory location addressed by
the ADDR lines passes through a transparent output latch
to the DO outputs. The timing for basic data access is
shown in the portions of Figure 9, Figure 10, and Figure 11
during which WE is Low.
Data can also be accessed on the DO outputs when assert-
ing the WE input. This is accomplished using two different
attributes:
Choosing the WRITE_FIRST attribute, data is written to the
addressed memory location on an enabled active CLK edge
and is also passed to the DO outputs. WRITE_FIRST timing
is shown in the portion of Figure 9 during which WE is High.
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