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Spartan-3 FPGA Family: DC and Switching Characteristics
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Table 17: Timing for the IOB Output Path
Speed Grade
-5
-4
Symbol
Description
Conditions
Max
Max
Units
Clock-to-Output Times
T_IOCKP
When reading from the
LVCMOS25⁽²⁾, 12mA
3.64
4.18
ns
Output Flip-Flop (OFF), the output drive, Fast slew
time from the active transition rate
at the OTCLK input to data
appearing at the Output pin
Propagation Times
T_IOOP
The time it takes for data to LVCMOS25⁽²⁾, 12mA
2.97
3.42
ns
travel from the IOB’s O input output drive, Fast slew
to the Output pin
rate
T_IOOLP
The time it takes for data to
travel from the O input
through the OFF latch to the
Output pin
3.41
3.92
ns
Set/Reset Times
T_IOSRP
Time from asserting the
LVCMOS25⁽²⁾, 12mA
4.44
5.10
ns
OFF’s SR input to
output drive, Fast slew
setting/resetting data at the rate
Output pin
T_IOGSRQ
Time from asserting the
Global Set Reset (GSR) net
to setting/resetting data at
the Output pin
8.07
9.28
ns
Notes:
1. The numbers in this table are tested using the methodology presented in Table 20 and are based on the operating conditions set
forth in Table 5 and Table 8.
2. This time requires adjustment whenever a signal standard other than LVCMOS25 with 12 mA drive and Fast slew rate is assigned
to the data Output. When this is true, add the appropriate Output adjustment from Table 19.
16
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