1N4007 Datasheet, PDF (99/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.6.3 Main PLL Control Register
The Main PLL uses two chip-level registers (MAINPLLCTL0 and MAINPLLCTL1) and the PLL controller
for its configuration. These MMRs exist inside the Bootcfg space. To write to these registers, software
should go through an unlocking sequence using KICK0/KICK1 registers. For valid configurable values into
the MAINPLLCTL0 and MAINPLLCTL1 Registers, see Section 6.25. See Section 8.3.4 for the address
location of the registers and locking and unlocking sequences for accessing the registers. The registers
are reset on POR only. MAINPLLCTL0 is shown in Figure 6-13 and described in Table 6-19.
MAINPLLCTL1 is shown in Figure 6-14 and described in Table 6-20.
Figure 6-13. Main PLL Control Register 0 (MAINPLLCTL0)
31
24
23
19
18
12
11
6
BWADJ[7:0]
Reserved
PLLM[12:6]
Reserved
RW-0000 0101
RW-0000 0
RW-0000000
RW-000000
Legend: RW = Read/Write; -n = value after reset
5
0
PLLD
RW-000000
Table 6-19. Main PLL Control Register 0 (MAINPLLCTL0) Field Descriptions
BIT FIELD
31-24 BWADJ[7:0]
23-19
18-12
11-6
5-0
Reserved
PLLM[12:6]
Reserved
PLLD
DESCRIPTION
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be
programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) -1
Reserved
A 13-bit bus that selects the values for the multiplication factor (see the following Note)
Reserved
A 6-bit bus that selects the values for the reference divider
Figure 6-14. Main PLL Control Register 1 (MAINPLLCTL1)
31
Reserved
RW-0000000000000000000000000
Legend: RW = Read/Write; -n = value after reset
7
6
ENSAT
RW-0
5
4
Reserved
RW-00
3
0
BWADJ[11:8]
RW-0000
Table 6-20. Main PLL Control Register 1 (MAINPLLCTL1) Field Descriptions
BIT
31-7
6
5-4
3-0
FIELD
Reserved
ENSAT
Reserved
BWADJ[11:8]
DESCRIPTION
Reserved
Needs to be set to 1 for proper operation of PLL
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be
programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) -1
NOTE
PLLM[5:0] bits of the multiplier are controlled by the PLLM Register inside the PLL controller
and PLLM[12:6] bits are controlled by the MAINPLLCTL0 chip-level register. The
MAINPLLCTL0 Register PLLM[12:6] bits should be written just before writing to the PLLM
Register PLLM[5:0] bits in the controller to have the complete 13-bit value latched when the
GO operation is initiated in the PLL controller. See the Phase-Locked Loop (PLL) for
KeyStone Devices User's Guide for the recommended programming sequence. Output divide
ratio and bypass enable/disable of the Main PLL is controlled by the SECCTL Register in the
PLL Controller. See the Section 6.6.2.1 for more details.
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