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| 1N4007 Datasheet, PDF (57/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A | |||
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TMS320C6652, TMS320C6654
SPRS841D â MARCH 2012 â REVISED JUNE 2016
5.7.11 EMIF16 Peripheral
The EMIF16 module provides an interface between DSP and external memories such as NAND and NOR
flash. For more information, see the External Memory Interface (EMIF16) for KeyStone Devices User's
Guide.
5.7.11.1 EMIF16 Electrical Data/Timing
Table 5-15. EMIF16 Asynchronous Memory Timing Requirements(1)(2)
(See Figure 5-17 and Figure 5-18.)
NO.
MIN
MAX UNIT
General Timing
2
tw(WAIT)
28
td(WAIT-WEH)
14
td(WAIT-OEH)
Pulse duration, WAIT assertion and deassertion minimum time
Setup time, WAIT asserted before WE high
Setup time, WAIT asserted before OE high
Read Timing
2E ns
4E + 3 ns
4E + 3 ns
3
tC(CEL)
EMIF read cycle time when ew = 0, meaning not in extended wait mode
(RS+RST+RH+3 (RS+RST+RH+3 ns
)*E-3
)*E+3
3
tC(CEL)
EMIF read cycle time when ew =1, meaning extended wait mode enabled
(RS+RST+WAIT (RS+RST+WAIT ns
+RH+3)*E-3
+RH+3)*E+3
4
tosu(CEL-OEL)
Output setup time from CE low to OE low. SS = 0, not in select strobe mode
5
toh(OEH-CEH)
Output hold time from OE high to CE high. SS = 0, not in select strobe mode
4
tosu(CEL-OEL)
Output setup time from CE low to OE low in select strobe mode, SS = 1
5
toh(OEH-CEH)
Output hold time from OE high to CE high in select strobe mode, SS = 1
6
tosu(BAV-OEL)
Output setup time from BA valid to OE low
7
toh(OEH-BAIV)
Output hold time from OE high to BA invalid
8
tosu(AV-OEL)
Output setup time from A valid to OE low
9
toh(OEH-AIV)
Output hold time from OE high to A invalid
10
tw(OEL)
OE active time low, when ew = 0. Extended wait mode is disabled.
10
tw(OEL)
OE active time low, when ew = 1. Extended wait mode is enabled.
11 td(WAITH-OEH) Delay time from WAIT deasserted to OE high
12
tsu(D-OEH)
Input setup time from D valid to OE high
13
th(OEH-D)
Input hold time from OE high to D invalid
Write Timing
(RS+1) * E - 3 (RS+1) * E + 3 ns
(RH+1) * E - 3 (RH+1) * E + 3 ns
(RS+1) * E - 3 (RS+1) * E + 3 ns
(RH+1) * E - 3 (RH+1) * E + 3 ns
(RS+1) * E - 3 (RS+1) * E + 3 ns
(RH+1) * E - 3 (RH+1) * E + 3 ns
(RS+1) * E - 3 (RS+1) * E + 3 ns
(RH+1) * E - 3 (RH+1) * E + 3 ns
(RST+1) * E - 3 (RST+1) * E + 3 ns
(RST+1) * E - 3 (RST+1) * E + 3 ns
4E + 3 ns
3
ns
0.5
ns
15
tc(CEL)
EMIF write cycle time when ew = 0, meaning not in extended wait mode
(WS+WST+WH+ (WS+WST+WH+ ns
3)*E-3
3)*E+3
15
tc(CEL)
EMIF write cycle time when ew =1., meaning extended wait mode is enabled
(WS+WST+WAI (WS+WST+WAI ns
T+WH+3)*E-3 T+WH+3)*E+3
16
tosuCEL-WEL)
Output setup time from CE low to WE low. SS = 0, not in select strobe mode
17
toh(WEH-CEH)
Output hold time from WE high to CE high. SS = 0, not in select strobe mode
16
tosuCEL-WEL)
Output setup time from CE low to WE low in select strobe mode, SS = 1
17
toh(WEH-CEH)
Output hold time from WE high to CE high in select strobe mode, SS = 1
18
tosu(RNW-WEL)
Output setup time from RNW valid to WE low
19
toh(WEH-RNW)
Output hold time from WE high to RNW invalid
20
tosu(BAV-WEL)
Output setup time from BA valid to WE low
21
toh(WEH-BAIV)
Output hold time from WE high to BA invalid
22
tosu(AV-WEL)
Output setup time from A valid to WE low
23
toh(WEH-AIV)
Output hold time from WE high to A invalid
24
tw(WEL)
WE active time low, when ew = 0. Extended wait mode is disabled.
24
tw(WEL)
WE active time low, when ew = 1. Extended wait mode is enabled.
26
tosu(DV-WEL)
Output setup time from D valid to WE low
27
toh(WEH-DIV)
Output hold time from WE high to D invalid
25 td(WAITH-WEH) Delay time from WAIT deasserted to WE high
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
(WST+1) * E - 3
(WST+1) * E - 3
(WS+1) * E - 3
(WH+1) * E - 3
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
4E + 3 ns
(1) E = 1/SYSCLK7, RS = Read Setup, RST = Read Strobe, RH = Read Hold, WS = Write Setup, WST = Write Strobe, WH = Write Hold.
(2) WAIT = number of cycles wait is asserted between the programmed end of the strobe period and wait deassertion.
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