1N4007 Datasheet, PDF (72/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
6.3.1 Power-Supply Sequencing
This section defines the requirements for a power up sequencing from a power-on reset condition. There
are two acceptable power sequences for the device. The first sequence stipulates the core voltages
starting before the I/O voltages as follows:
1. CVDD
2. CVDD1, VDDT1-2
3. DVDD18, AVDDA1, AVDDA2
4. DVDD15, VDDR1-4
The second sequence provides compatibility with other TI processors with the I/O voltage starting before
the core voltages as follows:
1. DVDD18, AVDDA1, AVDDA2
2. CVDD
3. CVDD1, VDDT1-2
4. DVDD15, VDDR1-4
The clock input buffers for CORECLK, DDRCLK, SGMIICLK (C6654 only), and PCIECLK (C6654 only)
use only CVDD as a supply voltage. These clock inputs are not fail-safe and must be held in a high-
impedance state until CVDD is at a valid voltage level. Driving these clock inputs high before CVDD is
valid could cause damage to the device. Once CVDD is valid it is acceptable that the P and N legs of
these CLKs may be held in a static state (either high and low or low and high) until a valid clock frequency
is needed at that input. To avoid internal oscillation the clock inputs should be removed from the high
impedance state shortly after CVDD is present.
If a clock input is not used it must be held in a static state. To accomplish this the N leg should be pulled
to ground through a 1 kΩ resistor. The P leg should be tied to CVDD to ensure it will not have any voltage
present until CVDD is active. Connections to the I/O cells powered by DVDD18 and DVDD15 are not fail-
safe and should not be driven high before these voltages are active. Driving these I/O cells high before
DVDD18 or DVDD15 are valid could cause damage to the device.
The device initialization is broken into two phases. The first phase consists of the time period from the
activation of the first power supply until the point in which all supplies are active and at a valid voltage
level. Either of the sequencing scenarios described above can be implemented during this phase.
Figure 6-1 and Figure 6-2 show both the core-before-I/O voltage sequence and the I/O-before-core
voltage sequence. POR must be held low for the entire power stabilization phase.
This is followed by the device initialization phase. The rising edge of POR followed by the rising edge of
RESETFULL will trigger the end of the initialization phase but both must be inactive for the initialization to
complete. POR must always go inactive before RESETFULL goes inactive as described in the following
sections. SYSCLK1 in the following section refers to the clock input that has been selected as the source
for the main PLL and SYSCLK1 refers to the main PLL output that is used by the CorePac, see Figure 6-3
for more details.
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Detailed Description
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