1N4007 Datasheet, PDF (100/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
6.6.4 Main PLL and PLL Controller Initialization Sequence
See the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide for details on the initialization
sequence for Main PLL and PLL Controller.
6.7 DDR3 PLL
The DDR3 PLL generates interface clocks for the DDR3 memory controller. When coming out of power-on
reset, the DDR3 PLL is programmed to a valid frequency during the boot config before being enabled and
used.
DDR3 PLL power is supplied externally through the Main PLL power-supply pin (AVDDA2). An external
EMI filter circuit must be added to all PLL supplies. See the Hardware Design Guide for KeyStone
Devices. For the best performance, TI recommends placing all the PLL external components on one side
of the board without jumpers, switches, or components other than those shown. For reduced PLL jitter,
maximize the spacing between switching signal traces and the PLL external components (C1, C2, and the
EMI Filter).
Figure 6-15 shows the DDR3 PLL.
DDRCLK(N|P)
DDR3 PLL
PLLD xPLLM /2
0
PLLOUT
DDR3
PHY
1
BYPASS
Figure 6-15. DDR3 PLL Block Diagram
6.7.1 DDR3 PLL Control Register
The DDR3 PLL, which is used to drive the DDR PHY for the EMIF, does not use a PLL controller. The
DDR3 PLL can be controlled using the DDR3PLLCTL0 and DDR3PLLCTL1 Registers in the Bootcfg
module. These MMRs exist inside the Bootcfg space. To write to these registers, software should go
through an unlocking sequence using the KICK0/KICK1 registers. For suggested configurable values, see
Section 8.3.4 for the address location of the registers and locking and unlocking sequences for accessing
the registers. This register is reset on POR only. DDR3PLLCTL0 is shown in Figure 6-16 and described in
Table 6-21. DDR3PLLCTL1 is shown in Figure 6-17 and described in Table 6-22.
Figure 6-16. DDR3 PLL Control Register 0 (DDR3PLLCTL0)⁽¹⁾
31
24
23
22
19
18
6
5
0
BWADJ[7:0]
RW,+0000 1001
BYPASS
RW,+0
Reserved
RW,+0001
PLLM
RW,+0000000010011
PLLD
RW,+000000
Legend: RW = Read/Write; -n = value after reset
(1) This register is Reset on POR only. The regreset, reset and bgreset from PLL are all tied to a common pll0_ctrl_rst_n The pwrdn,
regpwrdn, bgpwrdn are all tied to common pll0_ctrl_to_pll_pwrdn.
100 Detailed Description
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654