1N4007 Datasheet, PDF (145/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.14.2 EMAC Peripheral Register Description(s)
The memory maps of the EMAC are shown in Table 6-52 through Table 6-57.
HEX ADDRESS
02C0 8000
02C0 8004
02C0 8008
02C0 800F
02C0 8010
02C0 8014
02C0 8018
02C0 801C
02C0 8020 - 02C0 807C
02C0 8080
02C0 8084
02C0 8088
02C0 808C
02C0 8090
02C0 8094
02C0 8098 - 02C0 819C
02C0 80A0
02C0 80A4
02C0 80A8
02C0 80AC
02C0 80B0
02C0 80B4
02C0 80B8
02C0 80BC
02C0 80C0 - 02C0 80FC
02C0 8100
02C0 8104
02C0 8108
02C0 810C
02C0 8110
02C0 8114
02C0 8118 - 02C0 811C
02C0 8120
02C0 8124
02C0 8128
02C0 812C
02C0 8130
02C0 8134
02C0 8138
02C0 813C
02C0 8140
02C0 8144
02C0 8148
02C0 814C
Table 6-52. Ethernet MAC (EMAC) Control Registers
ACRONYM
TXIDVER
TXCONTROL
TXTEARDOWN
-
RXIDVER
RXCONTROL
RXTEARDOWN
-
-
TXINTSTATRAW
TXINTSTATMASKED
TXINTMASKSET
TXINTMASKCLEAR
MACINVECTOR
MACEOIVECTOR
-
RXINTSTATRAW
RXINTSTATMASKED
RXINTMASKSET
RXINTMASKCLEAR
MACINTSTATRAW
MACINTSTATMASKED
MACINTMASKSET
MACINTMASKCLEAR
-
RXMBPENABLE
RXUNICASTSET
RXUNICASTCLEAR
RXMAXLEN
RXBUFFEROFFSET
RXFILTERLOWTHRESH
-
RX0FLOWTHRESH
RX1FLOWTHRESH
RX2FLOWTHRESH
RX3FLOWTHRESH
RX4FLOWTHRESH
RX5FLOWTHRESH
RX6FLOWTHRESH
RX7FLOWTHRESH
RX0FREEBUFFER
RX1FREEBUFFER
RX2FREEBUFFER
RX3FREEBUFFER
REGISTER NAME
Transmit Identification and Version Register
Transmit Control Register
Transmit Teardown register
Reserved
Receive Identification and Version Register
Receive Control Register
Receive Teardown Register
Reserved
Reserved
Transmit Interrupt Status (Unmasked) Register
Transmit Interrupt Status (Masked) Register
Transmit Interrupt Mask Set Register
Transmit Interrupt Mask Clear Register
MAC Input Vector Register
MAC End of Interrupt Vector Register
Reserved
Receive Interrupt Status (Unmasked) Register
Receive Interrupt Status (Masked) Register
Receive Interrupt Mask Set Register
Receive Interrupt Mask Clear Register
MAC Interrupt Status (Unmasked) Register
MAC Interrupt Status (Masked) Register
MAC Interrupt Mask Set Register
MAC Interrupt Mask Clear Register
Reserved
Receive Multicast/Broadcast/Promiscuous Channel Enable Register
Receive Unicast Enable Set Register
Receive Unicast Clear Register
Receive Maximum Length Register
Receive Buffer Offset Register
Receive Filter Low Priority Frame Threshold Register
Reserved
Receive Channel 0 Flow Control Threshold Register
Receive Channel 1 Flow Control Threshold Register
Receive Channel 2 Flow Control Threshold Register
Receive Channel 3 Flow Control Threshold Register
Receive Channel 4 Flow Control Threshold Register
Receive Channel 5 Flow Control Threshold Register
Receive Channel 6 Flow Control Threshold Register
Receive Channel 7 Flow Control Threshold Register
Receive Channel 0 Free Buffer Count Register
Receive Channel 1 Free Buffer Count Register
Receive Channel 2 Free Buffer Count Register
Receive Channel 3 Free Buffer Count Register
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Detailed Description 145