1N4007 Datasheet, PDF (104/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
Table 6-24 provides the configuration of the EDMA3 transfer controller present on the device.
Table 6-24. EDMA3 Transfer Controller Configuration
PARAMETER
FIFOSIZE
BUSWIDTH
DSTREGDEPTH
DBS
TC0
1024 bytes
16 bytes
4 entries
64 bytes
EDMA3 CC
TC1
TC2
512 bytes
512 bytes
16 bytes
16 bytes
4 entries
4 entries
64 bytes
64 bytes
TC3
1024 bytes
16 bytes
4 entries
64 bytes
6.8.4 EDMA3 Channel Synchronization Events
The EDMA3 supports up to 64 DMA channels for EDMA3_CC that can be used to service system
peripherals and to move data between system memories. DMA channels can be triggered by
synchronization events generated by system peripherals. Table 6-25 lists the source of the
synchronization event associated with each of the EDMA3_CC DMA channels. On the C6654 and C6652,
the association of each synchronization event and DMA channel is fixed and cannot be reprogrammed.
For more detailed information on the EDMA3 module and how EDMA3 events are enabled, captured,
processed, prioritized, linked, chained, and cleared, and so forth, see the Enhanced Direct Memory
Access 3 (EDMA3) for KeyStone Devices User's Guide.
EVENT
NUMBER
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
104 Detailed Description
Table 6-25. EDMA3_CC Events for C6654 and C6652
EVENT
Reserved
Reserved
TINT2L
TINT2H
URXEVT
UTXEVT
GPINT0
GPINT1
GPINT2
GPINT3
Reserved
Reserved
Reserved
Reserved
URXEVT_B
UTXEVT_B
SPIINT0
SPIINT1
SEMINT0
SEMINT1
SEMINT2
SEMINT3
TINT4L
TINT4H
TINT5L
EVENT DESCRIPTION
Timer2 interrupt low
Timer2 interrupt high
UART0 receive event
UART0 transmit event
GPIO interrupt
GPIO interrupt
GPIO Interrupt
GPIO interrupt
UART1 receive event
UART1 transmit event
SPI interrupt
SPI interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Semaphore interrupt
Timer4 interrupt low
Timer4 interrupt high
Timer5 interrupt low
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