1N4007 Datasheet, PDF (89/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.6.2 PLL Controller Memory Map
The memory map of the PLL controller is shown in Table 6-9. C6654 and C6652-specific PLL Controller
register definitions can be found in the sections following Table 6-9. For other registers in the table, see
the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide.
NOTE
Only registers documented here are accessible on the C6654 and C6652. Other addresses
in the PLL controller memory map including the reserved registers should not be modified.
Furthermore, only the bits within the registers described here are supported. Avoid writing to
any reserved memory location or changing the value of reserved bits. It is recommended to
use read-modify-write sequence to make any changes to the valid bits in the register.
Table 6-9. PLL Controller Registers (Including Reset Controller)
HEX ADDRESS RANGE
0231 0000 - 0231 00E3
0231 00E4
0231 00E8
0231 00EC
0231 00F0
0231 00F0 - 0231 00FF
0231 0100
0231 0104
0231 0108
0231 010C
0231 0110
0231 0114
0231 0118
0231 011C
0231 0120
0231 0124
0231 0128
0231 012C - 0231 0134
0231 0138
0231 013C
0231 0140
0231 0144
0231 0148
0231 014C
0231 0150
0231 0154 - 0231 015C
0231 0160
0231 0164
0231 0168
0231 016C
0231 0170
0231 0174 - 0231 0193
0231 0194 - 0231 01FF
FIELD
-
RSTYPE
RSTCTRL
RSTCFG
RSISO
-
PLLCTL
-
SECCTL
-
PLLM
-
PLLDIV1
PLLDIV2
PLLDIV3
-
-
-
PLLCMD
PLLSTAT
ALNCTL
DCHANGE
CKEN
CKSTAT
SYSTAT
-
PLLDIV4
PLLDIV5
PLLDIV6
PLLDIV7
PLLDIV8
PLLDIV9 - PLLDIV16
-
REGISTER NAME
Reserved
Reset Type Status Register (Reset Controller)
Software Reset Control Register (Reset Controller)
Reset Configuration Register (Reset Controller)
Reset Isolation Register (Reset Controller)
Reserved
PLL Control Register
Reserved
PLL Secondary Control Register
Reserved
PLL Multiplier Control Register
Reserved
Reserved
PLL Controller Divider 2 Register
Reserved
Reserved
Reserved
Reserved
PLL Controller Command Register
PLL Controller Status Register
PLL Controller Clock Align Control Register
PLLDIV Ratio Change Status Register
Reserved
Reserved
SYSCLK Status Register
Reserved
Reserved
PLL Controller Divider 5 Register
Reserved
Reserved
PLL Controller Divider 8 Register
Reserved
Reserved
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Detailed Description
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