1N4007 Datasheet, PDF (119/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.9.2 CIC Registers
This section includes the offsets for CIC registers. The base addresses for interrupt control registers are
CIC0 - 0x0260 0000 and CIC1 - 0x0260 4000.
6.9.2.1 CIC0 Register Map
Table 6-29 describes the CIC0 registers.
ADDRESS
OFFSET
0x0
0x4
0xc
0x10
0x20
0x24
0x28
0x2c
0x34
0x38
0x200
0x204
0x208
0x20c
0x210
0x214
0x218
0x280
0x284
0x288
0x28c
0x290
0x294
0x298
0x300
0x304
0x308
0x30c
0x310
0x314
0x318
0x380
0x384
0x388
0x38c
0x390
0x394
0x398
0x400
Table 6-29. CIC0 Register
REGISTER MNEMONIC
REVISION_REG
CONTROL_REG
HOST_CONTROL_REG
GLOBAL_ENABLE_HINT_REG
STATUS_SET_INDEX_REG
STATUS_CLR_INDEX_REG
ENABLE_SET_INDEX_REG
ENABLE_CLR_INDEX_REG
HINT_ENABLE_SET_INDEX_REG
HINT_ENABLE_CLR_INDEX_REG
RAW_STATUS_REG0
RAW_STATUS_REG1
RAW_STATUS_REG2
RAW_STATUS_REG3
RAW_STATUS_REG4
RAW_STATUS_REG5
RAW_STATUS_REG6
ENA_STATUS_REG0
ENA_STATUS_REG1
ENA_STATUS_REG2
ENA_STATUS_REG3
ENA_STATUS_REG4
ENA_STATUS_REG5
ENA_STATUS_REG6
ENABLE_REG0
ENABLE_REG1
ENABLE_REG2
ENABLE_REG3
ENABLE_REG4
ENABLE_REG5
ENABLE_REG6
ENABLE_CLR_REG0
ENABLE_CLR_REG1
ENABLE_CLR_REG2
ENABLE_CLR_REG3
ENABLE_CLR_REG4
ENABLE_CLR_REG5
ENABLE_CLR_REG6
CH_MAP_REG0
REGISTER NAME
Revision Register
Control Register
Host Control Register
Global Host Int Enable Register
Status Set Index Register
Status Clear Index Register
Enable Set Index Register
Enable Clear Index Register
Host Int Enable Set Index Register
Host Int Enable Clear Index Register
Raw Status Register 0
Raw Status Register 1
Raw Status Register 2
Raw Status Register 3
Raw Status Register 4
Raw Status Register 5
Raw Status Register 6
Enabled Status Register 0
Enabled Status Register 1
Enabled Status Register 2
Enabled Status Register 3
Enabled Status Register 4
Enabled Status Register 5
Enabled Status Register 6
Enable Register 0
Enable Register 1
Enable Register 2
Enable Register 3
Enable Register 4
Enable Register 5
Enable Register 6
Enable Clear Register 0
Enable Clear Register 1
Enable Clear Register 2
Enable Clear Register 3
Enable Clear Register 4
Enable Clear Register 5
Enable Clear Register 6
Interrupt Channel Map Register for 0 to 0+3
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Detailed Description 119