1N4007 Datasheet, PDF (187/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
Global addresses are accessible to all masters in the system. In addition, local memory can be accessed
directly by the associated processor through aliased addresses, where the eight MSBs are masked to
zero. The aliasing is handled within the C66x CorePac and allows for common code to be run unmodified
on multiple cores. For example, address location 0x10800000 is the global base address for C66x
CorePac Core 0's L2 memory. C66x CorePac Core 0 can access this location by either using 0x10800000
or 0x00800000. Any other master on the device must use 0x10800000 only. Conversely, 0x00800000 can
by used by any of the cores as their own L2 base addresses.
For C66x CorePac Core 0, address 0x00800000 is equivalent to 0x10800000. Local addresses should be
used only for shared code or data, allowing a single image to be included in memory. Any code/data
targeted to a specific core, or a memory region allocated during run-time by a particular core should
always use the global address only.
7.1.4 MSM Controller
The MSM configuration for the device is as follows:
• Allows extension of external addresses from 2GB to up to 8GB
• Has built in memory protection features
For more details on external memory address extension and memory protection features, see the
Multicore Shared Memory Controller (MSMC) for KeyStone Devices User's Guide.
7.1.5 L3 Memory
The L3 ROM on the device is 128KB. The ROM contains software used to boot the device. There is no
requirement to block accesses from this portion to the ROM.
7.2 Memory Protection
Memory protection allows an operating system to define who or what is authorized to access L1D, L1P,
and L2 memory. To accomplish this, the L1D, L1P, and L2 memories are divided into pages. There are 16
pages of L1P (2KB each), 16 pages of L1D (2KB each), and 32 pages of L2 (16KB each). The L1D, L1P,
and L2 memory controllers in the C66x CorePac are equipped with a set of registers that specify the
permissions for each memory page.
Each page may be assigned with fully orthogonal user and supervisor read, write, and execute
permissions. In addition, a page may be marked as either (or both) locally accessible or globally
accessible. A local access is a direct DSP access to L1D, L1P, and L2, while a global access is initiated
by a DMA (either IDMA or the EDMA3) or by other system masters. EDMA or IDMA transfers programmed
by the DSP count as global accesses.
The DSP and each of the system masters on the device are all assigned a privilege ID. It is possible to
specify whether memory pages are locally or globally accessible.
The AIDx and LOCAL bits of the memory protection page attribute registers specify the memory page
protection scheme, see Table 7-1.
Table 7-1. Available Memory Page Protection Schemes
AIDx BIT
0
0
1
1
LOCAL BIT DESCRIPTION
0
No access to memory page is permitted.
1
Only direct access by DSP is permitted.
0
Only accesses by system masters and IDMA are permitted (includes EDMA
and IDMA accesses initiated by the DSP).
1
All accesses permitted.
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