1N4007 Datasheet, PDF (62/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
5.7.15 McBSP Electrical Data/Timing
The following tables assume testing over recommended operating conditions.
5.7.15.1 McBSP Timing
Table 5-22. McBSP Timing Requirements⁽¹⁾
(See Figure 5-25.)
NO.
2 t_c(CKRX)
3 t_w(CKRX)
5 t_su(FRH-CKRL)
Cycle time, CLKR/X
Pulse duration, CLKR/X high or CLKR/X low
Setup time, external FSR high before CLKR low
CLKR/X ext
CLKR/X ext
CLKR int
CLKR ext
MIN
2P or 20 ⁽²⁾⁽³⁾
P-1 ⁽⁴⁾
14
4
MAX
UNIT
ns
ns
ns
6 t_h(CKRL-FRH)
Hold time, external FSR high after CLKR low
CLKR int
CLKR ext
6
ns
3
7 t_su(DRV-CKRL) Setup time, DR valid before CLKR low
CLKR int
CLKR ext
14
ns
4
8 t_h(CKRL-DRV)
Hold time, DR valid after CLKR low
CLKR int
CLKR ext
3
ns
3
10 t_su(FXH-CKXL)
Setup time, external FSX high before CLKX low
CLKR int
CLKR ext
14
ns
4
11 t_h(CKXL-FXH)
Hold time, external FSX high after CLKX low
CLKR int
CLKR ext
6
ns
3
(1) CLKRP = CLKXP = FSRP = FSXP = 0. If polarity of any of the signals is inverted, then the timing references of that signal are also
inverted.
(2) P = SYSCLK7 period in ns. For example, when the SYSCLK7 clock domain is running at 166MHz, use 6ns.
(3) Use whichever value is greater. Minimum CLKR/X cycle times must be met, even when CLKR/X is generated by an internal clock
source. The minimum CLKR/X cycle times are based on internal logic speed; the maximum usable speed may be lower due to EDMA
limitations and AC timing requirements
(4) This parameter applies to the maximum McBSP frequency. Operate serial clocks (CLKR/X) in the reasonable range of 40/60 duty cycle.
62
Specifications
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654