1N4007 Datasheet, PDF (101/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
BIT FIELD
31-24 BWADJ[7:0]
23
BYPASS
22-19
18-6
5-0
Reserved
PLLM
PLLD
Table 6-21. DDR3 PLL Control Register 0 Field Descriptions
DESCRIPTION
BWADJ[11:8] and BWADJ[7:0] are located in DDR3PLLCTL0 and DDR3PLLCTL1 registers. The combination
(BWADJ[11:0]) should be programmed to a value related to PLLM[12:0] value based on the equation: BWADJ
= ((PLLM+1)>>1) -1
Enable bypass mode
• 0 = Bypass disabled
• 1 = Bypass enabled
Reserved
A 13-bit bus that selects the values for the multiplication factor
A 6-bit bus that selects the values for the reference divider
Figure 6-17. DDR3 PLL Control Register 1 (DDR3PLLCTL1)
31
14
13
12
Reserved
PLLRST
RW-000000000000000000
RW-0
Legend: RW = Read/Write; -n = value after reset
7
Reserved
RW-000000
6
ENSAT
RW-0
5
4
Reserved
R-0
3
0
BWADJ[11:8]
RW-0000
BIT
31-14
13
FIELD
Reserved
PLLRST
12-7
6
5-4
3-0
Reserved
ENSAT
Reserved
BWADJ[11:8]
Table 6-22. DDR3 PLL Control Register 1 Field Descriptions
DESCRIPTION
Reserved
PLL reset bit.
• 0 = PLL reset is released.
• 1 = PLL reset is asserted.
Reserved
Needs to be set to 1 for proper operation of the PLL
Reserved
BWADJ[11:8] and BWADJ[7:0] are located in separate registers. The combination (BWADJ[11:0]) should be
programmed to a value related to PLLM[12:0] value based on the equation: BWADJ = ((PLLM+1)>>1) -1
6.7.2 DDR3 PLL Device-Specific Information
As shown in Figure 6-15, the output of DDR3 PLL (PLLOUT) is divided by 2 and directly fed to the DDR3
memory controller. The DDR3 PLL is affected by power-on reset. During power-on resets, the internal
clocks of the DDR3 PLL are affected as described in Section 6.5. The DDR3 PLL is unlocked only during
the power-up sequence and is locked by the time the RESETSTAT pin goes high. It does not lose lock
during any of the other resets.
6.7.3 DDR3 PLL Initialization Sequence
See the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide for details on the initialization
sequence for DDR3 PLL.
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Detailed Description 101