1N4007 Datasheet, PDF (102/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
6.8 Enhanced Direct Memory Access (EDMA3) Controller
The primary purpose of the EDMA3 is to service user-programmed data transfers between two memory-
mapped slave endpoints on the device. The EDMA3 services software-driven paging transfers (for
example, data movement between external memory and internal memory), performs sorting or subframe
extraction of various data structures, services event driven peripherals, and offloads data transfers from
the device CPU.
There is one EDMA Channel Controller on the C6654 and C6652 devices: EDMA3_CC. It has four
transfer controllers: TC0, TC1, TC2, and TC3. In the context of this document, TCx associated with CC is
referred to as EDMA3_CC_TCx. Each of the transfer controllers has a direct connection to the switch
fabric. Section 9.2 lists the peripherals that can be accessed by the transfer controllers.
The EDMA3 Channel Controller includes the following features:
• Fully orthogonal transfer description
– Three transfer dimensions:
• Array (multiple bytes)
• Frame (multiple arrays)
• Block (multiple frames)
– Single event can trigger transfer of array, frame, or entire block
– Independent indexes on source and destination
• Flexible transfer definition:
– Increment or FIFO transfer addressing modes
– Linking mechanism allows for ping-pong buffering, circular buffering, and repetitive/continuous
transfers, all with no CPU intervention
– Chaining allows multiple transfers to execute with one event
• 512 PaRAM entries
– Used to define transfer context for channels
– Each PaRAM entry can be used as a DMA entry, QDMA entry, or link entry
• 64 DMA channels
– Manually triggered (CPU writes to channel controller register), external event triggered, and chain
triggered (completion of one transfer triggers another)
• Eight Quick DMA (QDMA) channels
– Used for software-driven transfers
– Triggered upon writing to a single PaRAM set entry
• Four transfer controllers and four event queues with programmable system-level priority
• Interrupt generation for transfer completion and error conditions
• Debug visibility
– Queue watermarking/threshold allows detection of maximum usage of event queues
– Error and status recording to facilitate debug
102 Detailed Description
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