1N4007 Datasheet, PDF (44/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
5.7 Timing and Switching Characteristics
5.7.1 SmartReflex
Increasing the device complexity increases its power consumption and with the smaller transistor
structures responsible for higher achievable clock rates and increased performance, comes an inevitable
penalty, increasing the leakage currents. Leakage currents are present in any active circuit, independently
of clock rates and usage scenarios. This static power consumption is mainly determined by transistor type
and process technology. Higher clock rates also increase dynamic power, the power used when
transistors switch. The dynamic power depends mainly on a specific usage scenario, clock rates, and I/O
activity.
TI's SmartReflex technology is used to decrease both static and dynamic power consumption while
maintaining the device performance. SmartReflex in the C6654 and C6652 devices is a feature that allows
the core voltage to be optimized based on the process corner of the device. This requires a voltage
regulator for each device.
To ensure maximizing performance and minimizing power consumption of the device, SmartReflex is
required to be implemented whenever the C6654 and C6652 devices are used. The voltage selection is
done using four VCNTL pins which are used to select the output voltage of the core voltage regulator.
For information on implementation of SmartReflex see the Power Management for KeyStone Devices
application report and the Hardware Design Guide for KeyStone Devices.
Table 5-1. SmartReflex 4-Pin VID Interface Switching Characteristics
(See Figure 5-1.)
NO.
PARAMETER
MIN
1
td(VCNTL[2:0]-VCNTL[3])
Delay Time - VCNTL[2:0] valid after VCNTL[3] low
2
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] low
0.07
3
td(VCNTL[2:0]-VCNTL[3])
Delay Time - VCNTL[2:0] valid after VCNTL[3] high
4
toh(VCNTL[3] -VCNTL[2:0]) Output Hold Time - VCNTL[2:0] valid after VCNTL[3] high
0.07
5
VCNTL being valid to CVDD being switched to SmartReflex Voltage⁽²⁾
(1) C = 1/SYSCLK1 frequency (see Figure 6-5) in ms
(2) SmartReflex voltage must be set before execution of application code
MAX
300.00
172020C ⁽¹⁾
300.00
172020C
10
UNIT
ns
ms
ns
ms
ms
CVDD
VCNTL[3]
VCNTL[2:0]
1.1 V
SRV*
* SRV = Smart Reflex Voltage
4
5
1
3
LSB VID[2:0]
MSB VID[5:3]
2
Figure 5-1. SmartReflex 4-Pin VID Interface Timing
44
Specifications
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654