1N4007 Datasheet, PDF (182/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
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6.25 PLL Boot Configuration Settings
The PLL default settings are determined by the BOOTMODE[12:10] bits. Table 6-90 shows settings for
various input clock frequencies.
Table 6-90. C66x DSP System PLL Configuration⁽¹⁾
850 MHz DEVICE
BOOTMODE [12:10]
INPUT CLOCK FREQ (MHz)
PLLD
PLLM
0b000
50.00
0
33
850
0b001
66.67
1
50
850.04
0b010
80.00
3
84
850
0b011
100.00
0
16
850
0b100
156.25
49
543
850
0b101
250.00
4
33
850
0b110
312.50
49
271
850
0b111
122.88
5
82
849.92
(1) The PLL boot configuration table above may not include all the frequency values that the device supports.
DSP ƒ
OUTPUT_DIVIDE is the value of the field of SECCTL[22:19]. This will set the PLL to the maximum clock
setting for the device (with OUTPUT_DIVIDE=2, by default).
• CLK = CLKIN × ((PLLM+1) ÷ ((OUTPUT_DIVIDE+1) × (PLLD+1)))
The Main PLL is controlled using a PLL controller and a chip-level MMR. The DDR3 PLL is controlled by
chip level MMRs. For details on how to set up the PLL see Section 6.6. For details on the operation of the
PLL controller module, see the Phase-Locked Loop (PLL) for KeyStone Devices User's Guide.
6.26 Second-Level Bootloaders
Any of the boot modes can be used to download a second-level bootloader. A second-level bootloader
allows for any level of customization to current boot methods as well as the definition of a completely
customized boot.
182 Detailed Description
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