1N4007 Datasheet, PDF (88/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
6.6.1 Main PLL Controller Device-Specific Information
6.6.1.1 Internal Clocks and Maximum Operating Frequencies
The Main PLL, used to drive the CorePacs, the switch fabric, and a majority of the peripheral clocks (all
but the DDR3) requires a PLL controller to manage the various clock divisions, gating, and
synchronization. The PLL controller of the Main PLL has several SYSCLK outputs that follow, as well as
the clock description. Each SYSCLK has a corresponding divider that divides down the output clock of the
PLL. Dividers are not programmable unless explicitly mentioned in the following description.
• SYSCLK1: Full-rate clock for the CorePac.
• SYSCLK2: 1/x-rate clock for CorePac emulation. The default rate for this is 1/3. It is programmable
from /1 to /32, where this clock does not violate the max of 350 MHz. The SYSCLK2 can be turned off
by software.
• SYSCLK3: 1/2-rate clock used to clock the MSMC and DDR EMIF.
• SYSCLK4: 1/3-rate clock for the switch fabrics and fast peripherals. The Debug_SS and ETBs use this
as well.
• SYSCLK5: 1/y-rate clock for the system trace module only. The default rate for this is 1/5. It is
configurable and the max configurable clock is 210 MHz and min configurable clock is 32 MHz. The
SYSCLK5 can be turned off by software.
• SYSCLK6: 1/64-rate clock. 1/64 rate clock (emif_ptv) used to clock the PVT-compensated buffers for
DDR3 EMIF.
• SYSCLK7: 1/6-rate clock for slow peripherals (GPIO, UART, Timer, I²C, SPI, EMIF16, McBSP, and so
forth.) and sources the SYSCLKOUT output pin.
• SYSCLK8: 1/z-rate clock. This clock is used as slow_sysclk in the system. Default is 1/64. It is
programmable from /24 to /80.
• SYSCLK9: 1/12-rate clock for SmartReflex.
• SYSCLK11: 1/6-rate clock for PSC only.
Only SYSCLK2, SYSCLK5, and SYSCLK8 are programmable on the C6654 and C6652 devices.
NOTE
In case any of the other programmable SYSCLKs are set slower than 1/64 rate, then
SYSCLK8 (SLOW_SYSCLK) must be programmed to either match, or be slower than, the
slowest SYSCLK in the system.
6.6.1.2 Main PLL Controller Operating Modes
The Main PLL controller has two modes of operation: bypass mode and PLL mode. The mode of
operation is determined by BYPASS bit of the PLL Secondary Control Register (SECCTL). In PLL mode,
SYSCLK1 is generated from the PLL output using the values set in PLLM and PLLD bit fields in the
MAINPLLCTL0 Register. In bypass mode, PLL input is fed directly out as SYSCLK1.
All hosts must hold off accesses to the DSP while the frequency of its internal clocks is changing. A
mechanism must be in place such that the DSP notifies the host when the PLL configuration has
completed.
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Detailed Description
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