1N4007 Datasheet, PDF (190/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
www.ti.com
8 Device Configuration
On the C6654 and C6652 devices, certain device configurations like boot mode and endianness, are
selected at device power-on reset. The status of the peripherals (enabled or disabled) is determined after
device power-on reset.
8.1 Device Configuration at Device Reset
Table 8-1 describes the device configuration pins. The logic level is latched at power-on reset to
determine the device configuration. The logic level on the device configuration pins can be set by using
external pullup or pulldown resistors or by using some control device (for example, FPGA/CPLD) to
intelligently drive these pins. When using a control device, ensure there is no contention on the lines when
the device is out of reset. The device configuration pins are sampled during power-on reset and are driven
after the reset is removed. To avoid contention, the control device must stop driving the device
configuration pins of the DSP. And when driving by a control device, the control device must be fully
powered and out of reset and driving the pins before the DSP can be taken out of reset.
Most of the device configuration pins are shared with other function pins (LENDIAN/GPIO[0],
BOOTMODE[12:0]/GPIO[13:1], PCIESSMODE[1:0]/GPIO[15:14], and PCIESSEN/TIMI0). Some time must
be given following the rising edge of reset to drive these device configuration input pins before they
assume an output state (those GPIO pins should not become outputs during boot). Also be aware that
systems using TIMI0 (the pin shared with PCIESSEN) as a clock input must assure that the clock is
disabled from the input until after reset is released and a control device is no longer driving that input.
NOTE
If a configuration pin must be routed out from the device and it is not driven (Hi-Z state), the
internal pullup or pulldown (IPU/IPD) resistor should not be relied upon. TI recommends the
use of an external pullup or pulldown resistor. For more detailed information on pullup or
pulldown resistors and situations in which external pullup or pulldown resistors are required,
see Section 8.4.
Table 8-1. C6654 and C6652 Device Configuration Pins
CONFIGURATION PIN
LENDIAN ^{(1) (2)}
BOOTMODE[12:0] ^{(1) (2)}
PCIESSMODE[1:0] ⁽¹⁾⁽²⁾
PCIESSEN ^{(1) (2)}
PIN NO.
T25
IPD/IPU ⁽¹⁾
IPU
R25, R3, U25,
IPD
T23, U24, T22,
R21, U22,
U23, V23,
U21, T21, V22
W21, V21
IPD
AD20
IPD
FUNCTIONAL DESCRIPTION
Device endian mode (LENDIAN).
• 0 = Device operates in big-endian mode
• 1 = Device operates in little-endian mode
Method of boot.
Some pins may not be used by bootloader and can be used as general purpose
config pins. See Bootloader for the C66x DSP User's Guide for how to determine
the device enumeration ID value.
PCIe Subsystem mode selection. (C6654 Only)
• 00 = PCIe in end point mode
• 01 = PCIe legacy end point (support for legacy INTx)
• 10 = PCIe in root complex mode
• 11 = Reserved
PCIe subsystem enable/disable. (C6654 Only)
• 0 = PCIE Subsystem is disabled
• 1 = PCIE Subsystem is enabled
(1) Internal 100-µA pulldown or pullup is provided for this terminal. In most systems, a 1-kΩ resistor can be used to oppose the IPD/IPU.
For more detailed information on pulldown or pullup resistors and situations in which external pulldown or pullup resistors are required,
see Section 8.4.
(2) These signal names are the secondary functions of these pins.
190 Device Configuration
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654