1N4007 Datasheet, PDF (73/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

www.ti.com
TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.3.1.1 Core-Before-IO Power Sequencing
Figure 6-1 shows the power sequencing and reset control of C6654 and C6652 for device initialization.
POR may be removed after the power has been stable for the required 100 µs. RESETFULL must be held
low for a period after the rising edge of POR but may be held low for longer periods if necessary. The
configuration bits shared with the GPIO pins will be latched on the rising edge of RESETFULL and must
meet the setup and hold times specified. SYSCLK1 must always be active before POR can be removed.
Core-before-IO power sequencing is defined in Table 6-2.
NOTE
TI recommends a maximum of 100 ms between one power rail being valid, and the next
power rail in the sequence starting to ramp.
POR
Power Stabilization Phase Device Initialization Phase
RESETFULL
GPIO Config
Bits
RESET
1
CVDD
4b
2c
2a
CVDD1
3
DVDD18
4a
DVDD15
SYSCLK1P&N
2b
DDRCLKP&N
6
5
7
8
9
10
RESETSTAT
Figure 6-1. Core-Before-IO Power Sequencing
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654
Detailed Description
73