1N4007 Datasheet, PDF (55/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

www.ti.com
TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
5.7.10 UART Peripheral
The universal asynchronous receiver/transmitter (UART) module provides an interface between the DSP
and a UART terminal interface or other UART-based peripheral. The UART is based on the industry
standard TL16C550 asynchronous communications element, which, in turn, is a functional upgrade of the
TL16C450. Functionally similar to the TL16C450 on power up (single character or TL16C450 mode), the
UART can be placed in an alternate FIFO (TL16C550) mode. This relieves the DSP of excessive software
overhead by buffering received and transmitted characters. The receiver and transmitter FIFOs store up to
16 bytes including three additional bits of error status per byte for the receiver FIFO.
The UART performs serial-to-parallel conversions on data received from a peripheral device and parallel-
to-serial conversion on data received from the DSP. The DSP can read the UART status at any time. The
UART includes control capability and a processor interrupt system that can be tailored to minimize
software management of the communications link. For more information on UART, see the Universal
Asynchronous Receiver/Transmitter (UART) for KeyStone Devices User's Guide.
Table 5-13. UART Timing Requirements
(See Figure 5-13 and Figure 5-14.)
NO.
Receive Timing
4
tw(RXSTART)
Pulse width, receive Start bit
5
tw(RXH)
Pulse width, receive data/parity bit high
5
tw(RXL)
Pulse width, receive data/parity bit low
6
tw(RXSTOP1)
Pulse width, receive Stop bit 1
6
tw(RXSTOP15)
Pulse width, receive Stop bit 1.5
6
tw(RXSTOP2)
Pulse width, receive Stop bit 2
Autoflow Timing Requirements
8
td(CTSL-TX)
Delay time, CTS asserted to Start bit transmit
(1) U = UART baud time = 1/programmed baud rate
(2) P = 1/SYSCLK7
MIN
MAX UNIT
0.96U ⁽¹⁾
1.05U ns
0.96U
1.05U ns
0.96U
1.05U ns
0.96U
1.05U ns
1.5*(0.96U) 1.5*(1.05U) ns
2*(0.96U)
2*(1.05U) ns
P ⁽²⁾
5P ns
4
5
5
6
RXD
Stop/Idle
Start
Bit 0
Bit 1
Bit N-1 Bit N
Parity
Stop
Idle
Start
Figure 5-13. UART Receive Timing Waveform
TXD
Bit N-1 Bit N
Stop
8
Start
Bit 0
CTS
Figure 5-14. UART CTS (Clear-to-Send Input) — Autoflow Timing Waveform
Copyright © 2012–2016, Texas Instruments Incorporated
Submit Documentation Feedback
Product Folder Links: TMS320C6652 TMS320C6654
Specifications
55