1N4007 Datasheet, PDF (48/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
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Table 5-7. DDR3 PLL DDRSYSCLK1(N|P) Timing Requirements
(See Figure 5-7 and Figure 5-6.)
NO
MIN
MAX UNIT
DDRCLK[P:N]
1 tc(DDRCLKN)
Cycle time _ DDRCLKN cycle time
3.2
25 ns
1 tc(DDRCLKP)
Cycle time _ DDRCLKP cycle time
3.2
25 ns
3 tw(DDRCLKN)
Pulse width _ DDRCLKN high
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN) ns
2 tw(DDRCLKN)
Pulse width _ DDRCLKN low
0.45*tc(DDRCLKN) 0.55*tc(DDRCLKN) ns
2 tw(DDRCLKP)
Pulse width _ DDRCLKP high
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP) ns
3 tw(DDRCLKP)
Pulse width _ DDRCLKP low
0.45*tc(DDRCLKP) 0.55*tc(DDRCLKP) ns
4 tr(DDRCLK_250mv) Transition time _ DDRCLK differential rise time (250 mV)
50
350 ps
4 tf(DDRCLK_250mv) Transition time _ DDRCLK differential fall time (250 mV)
50
350 ps
5 tj(DDRCLKN)
Jitter, peak_to_peak _ periodic DDRCLKN
0.025*tc(DDRCLKN) ps
5 tj(DDRCLKP)
Jitter, peak_to_peak _ periodic DDRCLKP
0.025*tc(DDRCLKP) ps
DDRCLKN
DDRCLKP
1
2
3
4
5
Figure 5-7. DDR3 PLL DDRCLK Timing
5.7.6 External Interrupts Electrical Data/Timing
Table 5-8. NMI and Local Reset Timing Requirements⁽¹⁾
(See Figure 5-8.)
NO.
1
tsu(LRESET-LRESETNMIENL)
Setup Time - LRESET valid before LRESETNMIEN low
1
tsu(NMI-LRESETNMIENL)
Setup Time - NMI valid before LRESETNMIEN low
1
tsu(CORESELn-LRESETNMIENL) Setup Time - CORESEL[2:0] valid before LRESETNMIEN low
2
th(LRESETNMIENL-LRESET)
Hold Time - LRESET valid after LRESETNMIEN high
2
th(LRESETNMIENL-NMI)
Hold Time - NMI valid after LRESETNMIEN high
2
th(LRESETNMIENL-CORESELn) Hold Time - CORESEL[2:0] valid after LRESETNMIEN high
3
tw(LRESETNMIEN)
Pulse Width - LRESETNMIEN low width
(1) P = 1/SYSCLK1 clock frequency in ns.
MIN
12*P
12*P
12*P
12*P
12*P
12*P
12*P
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
CORESEL[3:0]/
LRESET/
NMI
LRESETNMIEN
1
2
3
Figure 5-8. NMI and Local Reset Timing
48
Specifications
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