1N4007 Datasheet, PDF (1/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

Product
Folder
Sample &
Buy
Technical
Documents
Tools &
Software
Support &
Community
TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
TMS320C6652 and TMS320C6654 Fixed and Floating-Point Digital Signal Processor
1 Device Overview
1.1 Features
1
• One TMS320C66x DSP Core Subsystem
(CorePac)
– C66x Fixed- and Floating-Point CPU Core: Up
to 850 MHz for C6654 and 600 MHz for C6652
• Multicore Shared Memory Controller (MSMC)
– Memory Protection Unit for DDR3_EMIF
• Multicore Navigator
– 8192 Multipurpose Hardware Queues with
Queue Manager
– Packet-Based DMA for Zero-Overhead
Transfers
• Peripherals
– PCIe Gen2 (C6654 Only)
• Single Port Supporting 1 or 2 Lanes
• Supports up to 5 GBaud Per Lane
– Gigabit Ethernet (GbE) Subsystem (C6654
Only)
• One SGMII Port
• Supports 10-, 100-, and 1000-Mbps
Operation
– 32-Bit DDR3 Interface
• DDR3-1066
• 8GB of Addressable Memory Space
– 16-Bit EMIF
– Universal Parallel Port
• Two Channels of 8 Bits or 16 Bits Each
• Supports SDR and DDR Transfers
– Two UART Interfaces
– Two Multichannel Buffered Serial Ports
(McBSPs)
– I²C Interface
– 32 GPIO Pins
– SPI Interface
– Semaphore Module
– Eight 64-Bit Timers
– Two On-Chip PLLs
• Commercial Temperature:
– 0°C to 85°C
• Extended Temperature:
– –40°C to 100°C
1.2 Applications
• Power Protection Systems
• Avionics and Defense
• Currency Inspection and Machine Vision
• Medical Imaging
• Other Embedded Systems
• Industrial Transportation Systems
1.3 Description
The C6654 and C6652 are high performance fixed- and floating-point DSPs that are based on TI's
KeyStone multicore architecture. Incorporating the new and innovative C66x DSP core, this device can
run at a core speed of up to 850 MHz for C6654 and 600 MHz for C6652. For developers of a broad range
of applications, both C6654 and C6652 DSPs enable a platform that is power-efficient and easy to use. In
addition, the C6654 and C6652 DSPs are fully backward compatible with all existing C6000™ family of
fixed- and floating-point DSPs.
TI's KeyStone architecture provides a programmable platform integrating various subsystems (C66x cores,
memory subsystem, peripherals, and accelerators) and uses several innovative components and
techniques to maximize intradevice and interdevice communication that lets the various DSP resources
operate efficiently and seamlessly. Central to this architecture are key components such as Multicore
Navigator that allows for efficient data management between the various device components. The TeraNet
is a nonblocking switch fabric enabling fast and contention-free internal data movement. The multicore
shared memory controller allows access to shared and external memory directly without drawing from
switch fabric capacity.
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.