1N4007 Datasheet, PDF (95/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.6.2.6 Reset Type Status Register (RSTYPE)
The Reset Type Status (RSTYPE) Register latches the cause of the last reset. If multiple reset sources
occur simultaneously, this register latches the highest priority reset source. The Reset Type Status
Register is shown in Figure 6-9 and described in Table 6-15.
Figure 6-9. Reset Type Status Register (RSTYPE)
31
29
28
27
12
Reserved
EMU-
RST
Reserved
R-0
R-0
R-0
Legend: R = Read only; -n = value after reset
11
8
WDRST[N]
R-0
7
3
Reserved
R-0
2
PLLCTRL
RST
R-0
1
RESET
R-0
0
POR
R-0
BIT
31-29
28
FIELD
Reserved
EMU-RST
27-12 Reserved
11
WDRST3
10
WDRST2
9
WDRST1
8
WDRST0
7-3 Reserved
2
PLLCTLRST
1
RESET
0
POR
Table 6-15. Reset Type Status Register (RSTYPE) Field Descriptions
DESCRIPTION
Reserved. Read only. Always reads as 0. Writes have no effect.
Reset initiated by emulation.
• 0 = Not the last reset to occur.
• 1 = The last reset to occur.
Reserved. Read only. Always reads as 0. Writes have no effect.
Reset initiated by watchdog timer[N].
• 0 = Not the last reset to occur.
• 1 = The last reset to occur.
Reset initiated by watchdog timer[N].
• 0 = Not the last reset to occur.
• 1 = The last reset to occur.
Reset initiated by watchdog timer[N].
• 0 = Not the last reset to occur.
• 1 = The last reset to occur.
Reset initiated by watchdog timer[N].
• 0 = Not the last reset to occur.
• 1 = The last reset to occur.
Reserved. Read only. Always reads as 0. Writes have no effect.
Reset initiated by PLLCTL.
• 0 = Not the last reset to occur.
• 1 = The last reset to occur.
RESET reset.
• 0 = RESET was not the last reset to occur.
• 1 = RESET was the last reset to occur.
Power-on reset.
• 0 = Power-on reset was not the last reset to occur.
• 1 = Power-on reset was the last reset to occur.
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