1N4007 Datasheet, PDF (53/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
Table 5-12. SPI Switching Characteristics
(See Figure 5-11 and Figure 5-12.)
NO.
PARAMETER
MIN
MAX UNIT
Master Mode Timing Diagrams — Base Timings for 3-Pin Mode
1
tc(SPC)
Cycle Time, SPICLK, All Master Modes
3*P2 ⁽¹⁾
ns
2
tw(SPCH)
Pulse Width High, SPICLK, All Master Modes
0.5*tc - 1
ns
3
tw(SPCL)
Pulse Width Low, SPICLK, All Master Modes
0.5*tc - 1
ns
4
td(SDO-SPC)
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 0
5 ns
4
td(SDO-SPC)
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 0, Phase = 1
5 ns
4
td(SDO-SPC)
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 1, Phase = 0
5 ns
4
td(SDO-SPC)
Setup (Delay), initial data bit valid on SPIDOUT to initial edge on SPICLK.
Polarity = 1, Phase = 1
5 ns
5
td(SPC-SDO)
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK.. Polarity = 0 Phase = 0
2 ns
5
td(SPC-SDO)
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK. Polarity = 0 Phase = 1
2 ns
5
td(SPC-SDO)
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK. Polarity = 1 Phase = 0
2 ns
5
td(SPC-SDO)
Setup (Delay), subsequent data bits valid on SPIDOUT to initial edge on
SPICLK. Polarity = 1 Phase = 1
2 ns
6
toh(SPC-SDO) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final
0.5*tc - 2
ns
bit. Polarity = 0 Phase = 0
6
toh(SPC-SDO) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final
0.5*tc - 2
ns
bit. Polarity = 0 Phase = 1
6
toh(SPC-SDO) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final
0.5*tc - 2
ns
bit. Polarity = 1 Phase = 0
6
toh(SPC-SDO) Output hold time, SPIDOUT valid after receive edge of SPICLK except for final
0.5*tc - 2
ns
bit. Polarity = 1 Phase = 1
Additional SPI Master Timings — 4-Pin Mode with Chip Select Option
19 td(SCS-SPC)
Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 0
2*P2 - 5
2*P2 + 5 ns
19 td(SCS-SPC)
Delay from SPISCS[n] active to first SPICLK. Polarity = 0 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
19 td(SCS-SPC)
Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 0
2*P2 - 5
2*P2 + 5 ns
19 td(SCS-SPC)
Delay from SPISCS[n] active to first SPICLK. Polarity = 1 Phase = 1
0.5*tc + (2*P2) - 5 0.5*tc + (2*P2) + 5 ns
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0
Phase = 0
1*P2 - 5
1*P2 + 5 ns
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 0
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1
Phase = 0
1*P2 - 5
1*P2 + 5 ns
20 td(SPC-SCS)
Delay from final SPICLK edge to master deasserting SPISCS[n]. Polarity = 1
Phase = 1
0.5*tc + (1*P2) - 5 0.5*tc + (1*P2) + 5 ns
tw(SCSH)
Minimum inactive time on SPISCS[n] pin between two transfers when SPISCS[n]
2*P2 - 5
ns
is not held using the CSHOLD feature.
(1) P2 = 1/SYSCLK7
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Specifications
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