1N4007 Datasheet, PDF (163/236 Pages) Naina Semiconductor ltd. – General Purpose Rectifier 1.0A

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TMS320C6652, TMS320C6654
SPRS841D – MARCH 2012 – REVISED JUNE 2016
6.24 Boot Modes Supported and PLL Settings
The device supports several boot processes, which leverage the internal boot ROM. Most boot processes
are software driven, using the BOOTMODE[2:0] device configuration inputs to determine the software
configuration that must be completed. From a hardware perspective, there are two possible boot modes:
• ROM Boot - C66x CorePac0 is released from reset and begins executing from the L3 ROM base
address. After performing the boot process (for example, from I²C ROM, Ethernet, or RapidIO), C66x
CorePac0 then begins execution from the provided boot entry point. See the Bootloader for the C66x
DSP User's Guide for more details.
The boot process performed by the C66x CorePac0 in ROM boot is determined by the BOOTMODE[12:0]
value in the DEVSTAT register. The C66x CorePac0 reads this value, and then executes the associated
boot process in software. Figure 6-26 shows the bits associated with BOOTMODE[12:0].
Figure 6-26. Boot Mode Pin Decoding
12
11
10
9
8
7
6
5
4
3
2
1
0
PLL Mult I²C /SPI Ext Dev Cfg
Device Configuration
Boot Device
6.24.1 Boot Device Field
The Boot Device field BOOTMODE[2:0] defines the boot device that is chosen. Table 6-61 shows the
supported boot modes.
Bit Field
2-0 Boot Device
Table 6-61. Boot Mode Pins: Boot Device Values
Description
Device boot mode
• 0 = EMIF16 / UART / No Boot
• 1 = Reserved
• 2 = Ethernet (SGMII) (C6654 only)
• 3 = NAND
• 4 = PCIe (C6654 only)
• 5 = I²C
• 6 = SPI
• 7 = Reserved
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Detailed Description 163